Digital delay line

A digital delay line to supply from a periodic input signal n signals with the same period mutually phase-shifted by one n-th of the input signal period, including:

• n cells each of which includes m delay elements in series, each output of a delay element being connected to an input of a multiplexer, each multiplexer having an output that is one of the n signals;
• means for comparing the output phase of the n-th cell with the input signal phase to provide an error signal;
• and
• means for modifying the output of the multiplexer of one of the n cells in response to the error signal;
• wherein each delay element is formed by a NAND gate having an input that receives the signal to be delayed and the other input that receives an enabling signal.

A delay line that receives an input clock signal, having a period, to provide n output signals, the delay line comprising:

• an input terminal that receives the input clock signal;
• n output terminals, each output terminal providing a respective one of the n signals;
• n cells, electrically coupled to the input terminal, each one of the n cells coupled to a respective one of the n output terminals, and each cell receiving a cell input signal and providing a phase shift to the cell input signal to generate a cell output signal as a respective one of the n output signals, wherein each one of the n cells comprises:
• a series of m delay elements, each delay element providing a delayed output signal, a first delay element of the series receiving the cell input signal of the one of the n cells, and each delay element, aside from the first delay element, receiving the delayed output signal of a prior delay element in the series, wherein the series of m delay elements includes:
• a series of m NAND gates, each NAND gate having two input terminals and an output terminal that provides the delayed output signal, a first NAND gate of the series receiving the cell input signal at a first one of the two input terminals, and each NAND gate aside from the first NAND gate receiving the delayed output signal of a prior NAND gate in the series at a first one of the two input terminals;
• and
• m mask terminals, each one of the mask terminals being coupled to a respective one of the second one of the two input terminals of the m NAND gates;
• and
• a multiplexing unit coupled to each one of the m delay elements, the delayed output signal of the m delay elements being received as inputs by the multiplexing unit, a control signal selecting one delayed output signal from the inputs to be an output of the multiplexing unit, the output of the multiplexing unit being the cell output signal of the one of the n cells;
• and
• a control circuit coupled to the n cells that adjusts the phase shift through at least one of the n cells so that the phase shift through the at least one cell is substantially the period of the input clock signal divided by n.

A delay line that receives an input clock signal, having a period, to provide n output signals, the delay line comprising:

• an input terminal that receives the input clock signal;
• n output terminals, each output terminal providing a respective one of the n signals;
• n cells, electrically coupled to the input terminal, each one of the n cells coupled to a respective one of the n output terminals, and each cell receiving a cell input signal and providing a phase shift to the cell input signal to generate a cell output signal as a respective one of the n output signals;
• and
• a control circuit coupled to the n cells that adjusts the phase shift through at least one of the n cells, by providing respective control signals, to each cell, that select a respective number of digital delay elements that the cell input signal propagates through, so that the phase shift through each of the at least one cell is substantially the period of the input clock signal divided by n;
• wherein the control circuit compares the phase of the output signal of one of the n cells and of the input clock signal to provide an error signal and modifies the phase shift through at least one of the n cells based on the error signal, and wherein the control circuit further includes
• at least one select line coupled to the n cells for selecting at least one cell of the n cells to modify the phase shift provided by the at least one cell;
• and
• at least one control line coupled to the n cells for sending control signals that determine an amount of phase shift through the at least one cell.

A method of generating n signals given an input clock signal having a period, the method including the steps of:

• A. receiving the input clock signal;
• B. phase-shifting the input clock signal to generate n signals, each one of the n signals having a respective phase shift;
• C. forming an error signal, the error signal indicating whether each of the n signals are successively phase shifted from each other by substantially the period of the input clock signal divided by n;
• D. selecting a respective number of digital delay elements that each signal propagates through to set the respective phase shift, based on the error signal, so that each of the n signals are successively phase-shifted from each other by more substantially the period of the input clock signal divided by n;
• and delaying the step of selecting upon a change in the error signal until the n-signals are at respective predetermined states determined by the error signal before the change.

A delay line that receives an input clock signal having a period to provide n signals, each one of the n signals having a respective phase shift from the input clock signal, the delay line comprising:

• an input terminal that receives the input clock signal;
• a series of n output terminals, each output terminal providing a respective one of the n signals;
• n cells coupled to the input terminal and each one of the n cells coupled to a respective one of the n output terminals;
• means for maintaining a phase shift of a first signal of the n signals from a second signal of the n signals substantially at the period of the input clock signal divided by n, by selecting a respective number of digital delay elements in each of the n cells;
• and
• means for preventing glitches in the n signals by delaying control signals provided by the means for maintaining before the control signals reach the n-cells.

A delay line that receives an input clock signal having a period to provide n signals, each one of the n signals having a respective phase shift from the input clock signal, the delay line comprising:

• an input terminal that receives the input clock signal;
• a series of n output terminals, each output terminal providing a respective one of the n signals;
• n cells coupled to the input terminal and each one of the n cells coupled to a respective one of the n output terminals;
• means for maintaining a phase shift of a first signal of the n signals from a second signal of the n signals substantially at the period of the input clock signal divided by n;
• and
• means for minimizing a power consumption in the delay line.

A delay line that receives an input clock signal having a period to provide n signals, each one of the n signals having a respective phase shift from the input clock signal, the delay line comprising:

• an input terminal that receives the input clock signal;
• a series of n output terminals, each output terminal providing a respective one of the n signals;
• n cells coupled to the input terminal and each one of the n cells coupled to a respective one of the n output terminals;
• means for maintaining a phase shift of a first signal of the n signals from a second signal of the n signals substantially at the period of the input clock signal divided by n;
• and
• means for inhibiting metastable states in the delay line that is implemented digitally.

A delay line that receives an input clock signal having a period to provide n signals, each one of the n signals having a respective phase shift from the input clock signal, the delay line comprising:

• an input terminal that receives the input clock signal;
• a series of n output terminals, each output terminal providing a respective one of the n signals;
• n cells coupled to the input terminal and each one of the n cells coupled to a respective one of the n output terminals;
• means for maintaining a phase shift of a first signal of the n signals from a second signal of the n signals substantially at the period of the input clock signal divided by n, by providing respective control signals to each of the n cells individually via control terminals, each cell having control terminals that are separate and distinct from control terminals of other cells such that each cell can be controlled individually;
• and
• means for preventing glitches in the n signals by delaying signals provided by the means for maintaining before the signals reach the n-cells.

A delay line that receives an input clock signal having a period to provide n signals, each one of the n signals having a respective phase shift from the input clock signal, the delay line comprising:

• an input terminal that receives the input clock signal;
• a series of n output terminals, each output terminal providing a respective one of the n signals;
• n cells coupled to the input terminal and each one of the n cells coupled to a respective one of the n output terminals;
• means for maintaining a phase shift of a first signal of the n signals from a second signal of the n signals substantially at the period of the input clock signal divided by n, by providing respective control signals to each of the n cells individually via control terminals, each cell having control terminals that are separate and distinct from control terminals of other cells such that each cell can be controlled individually;
• and
• means for minimizing a power consumption in the delay line.