US 5,633,607 AGranted

Edge triggered set-reset flip-flop (SRFF)

AssigneeMosaid Technologies Incorporated

InventorBruce Millar

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Abstract

A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second latch.

Claims6

Dependent claims

A timer comprising:

(a) first and second gated SR (set-reset) latches each including two pair of inputs S1, S2 and R1, R2 and a pair of outputs Q, QN,
(b) the Q output of the first gated SR latch being connected to the R2 input of the second gated SR latch, and the QN output of the first gated SR latch being connected to the S2 input of the second gated SR latch,
(c) the Q output of the second gated SR latch being connected to the S2 input of the first gated SR latch, and the QN output of the second gated SR latch being connected to the R2 input of the first gated SR latch,
(d) means for applying a delayed representation of a first pulse signal to the S1 input of the first gated SR latch and means for applying a delayed representation of a second pulse signal to the R1 input of the first gated SR latch,
(e) means for applying an inverted representation of the first pulse signal to the S1 input of the second gated SR latch and means for applying an inverted representation of the second pulse signal to the R1 input of the second gated SR latch,
whereby output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second gated SR latch.

3 more elements

Dependencies are inferred from the claim text.