Data output buffer using pass transistors biased with a reference voltage and a precharged data input

A data output buffer circuit for a semiconductor device for transferring read cell data to peripheral circuits, comprising:

• an input terminal for inputting the read cell data;
• first data transfer means for transferring the data from said input terminal when it has a first logic level;
• second data transfer means for transferring the data from said input terminal when it has a second logic level;
• high logic transfer means for transferring a high logic signal in response to an output signal from said first data transfer means;
• low logic transfer means for transferring a low logic signal in response to an output signal from said second data transfer means;
• an output terminal for outputting the high logic signal from said high logic transfer means or the low logic signal from said low logic transfer means to the peripheral circuits;
• first operation control means connected between said first data transfer means and said high logic transfer means, for setting a level of the output signal from said first data transfer means to a supply voltage level in a standby mode to control the operation of said high logic transfer means;
• and
• second operation control means connected between said second data transfer means and said low logic transfer means, for setting a level of the output signal from said second data transfer means to a ground voltage level in the standby mode to control the operation of said low logic transfer means;
• wherein the data form said input terminal is initially precharged with half of a supply voltage level.

A data output buffer circuit for a semiconductor device for transferring read cell data to peripheral circuits, comprising:

• an input terminal for inputting the read cell data;
• first data transfer means for transferring the data from said input terminal when it has a first logic level;
• second data transfer means for transferring the data from said input terminal when it has a second logic level;
• high logic transfer means for transferring a high logic signal in response to an output signal from said first data transfer means;
• low logic transfer means for transferring a low logic signal in response to an output signal from said second data transfer means;
• an output terminal for outputting the high logic signal from said high logic transfer means or the low logic signal from said low logic transfer means to the peripheral circuits;
• first operation control means connected between said first data transfer means and said high logic transfer means, for setting a level of the output signal from said first data transfer means to a supply voltage level in a standby mode to control the operation of said high logic transfer means and for controlling an amount of current flowing through said high logic transfer means in an operation mode to transfer the high logic signal to said output terminal;
• and
• second operation control means connected between said second data transfer means and said low logic transfer means, for setting a level of the output signal from said second data transfer means to a ground voltage level in the standby mode to control the operation of said low logic transfer means and for controlling an amount of current flowing through said low logic transfer means in the operation mode to transfer the low logic signal to said output terminal.