US 5,633,601 A · Field programmable gate array logic module configurable as combinational or sequential circuits

Abstract

A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 1800 Boolean combinational functions on each output 431-432, to operate as a full adder with sum and carry outputs, or to form the sequential function of a D-latch or a D-flipflop. The logic module has ten input terminals 411-418, 421-422 and two output terminals 431-432. The logic module is comprised of two-input multiplexors 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100. The D-latch and D-flipflop have a preset input terminal 415 and a clear input terminal 414. Furthermore, the D-latch can be configured to be latched on either a low level or a high level clock signal on terminal 411, while the D-flipflop can be configured to be triggered by either a low to high transition or a high to low transition of a clock signal on terminal 411. A logic module 401 can be configured to provide both a Q and !Q outputs of the D-latch or D-flipflop on output terminals 431-432. A logic module 402 can be configured to additionally provide a circuit of two D-latches.

Claims19

Dependent claims

A logic module for use in a field programmable gate array integrated circuit comprising:

a plurality of input terminals, two output terminals, a plurality of logic elements, and an interconnection network interconnecting said input terminals, logic elements and output terminals;
said interconnection network and said logic elements being responsive to a first combination of signals on at least some of said input terminals to form a boolean combination circuit;
said interconnection network and said logic elements being responsive to a second combination of signals on at least some of said input terminals to form a full adder circuit;
said interconnection network and said logic elements being responsive to a third combination of signals on at least some of said input terminals to form a D-latch circuit that has a preset input and a clear input;
and
said interconnection network and said logic elements being responsive to a fourth combination of signals on at least some of said input terminals to form a D-flipflop circuit that has a preset input and a clear input.

3 more elements

A method for forming a logic module for use in a field programmable gate array integrated circuit comprising the steps of:

forming a logic module having a plurality of input terminals, a plurality of logic elements, and two output terminals;
interconnecting said logic elements within said logic module to said input terminals and said output terminals;
forming control circuitry within said logic module to selectively reconfigure said logic elements to form any one circuit selected from the group of circuits comprising a boolean combinational function generator, a full adder, a D-latch having a preset input and a dear input, or a D-flipflop having a preset input and a clear input connected to certain ones of said input terminals;
wherein the step of forming control circuitry within said logic module further comprises:
decoding a certain plurality of said input terminals of said logic module into a larger plurality of control states represented by a plurality of control signals;
and
using said control signals to reconfigure the logic elements within said logic module to form a logic circuit in accordance with said control state;
and
placing the output of said logic circuit on said output terminals.

6 more elements

A logic module for use in a field programmable gate array integrated circuit, comprising:

a logic module having a plurality of input terminals, two output terminals, a plurality of logic elements, and an interconnection network interconnecting said input terminals, logic elements and output terminals;
said logic module further comprising:
a first mux having an inverting 1-input connected to one of said input terminals, a 0-input connected to a second one of said input terminals, a select control connected to a third one of said input terminals, and an output;
a second mux having a 0-input connected to said output of said first mux, a 1-input connected to an output of a seventh mux, a select control connected to a first one of certain said input terminals designated as control input terminals, and an output;
a third mux having a 0-input connected to an output of a fourth mux, a 1-input connected to a sixth one of said input terminals, a select control connected to said output of said first mux, and an output;
said fourth mux having a 0-input connected to a seventh one of said input terminals, a 1-input connected to an output of a sixth mux, a select control connected to a second one of certain said input terminals designated as control input terminals, and an output;
a fifth mux having a 0-input connected to a fifth one of said input terminals, an inverting 1-input connected to a fourth one of said input terminals, a select control connected to said output of said second mux, and an output;
said sixth mux having a 0-input connected to said fifth one of said input terminals, an inverting 1-input connected to said fourth one of said input terminals, a select control connected to said output of said third mux, and an output;
said seventh mux having a 0-input connected to said output of said fifth mux, a 1-input connected to said output of said sixth mux, a select control connected to an output of a ninth mux, and an output connected to one of said output terminals;
an eighth mux having a 0-input connected to said output of said third mux, a 1-input connected to said output of said fifth mux, a select control connected to an eighth one of said input terminals, and an output connected to a second one of said output terminals;
and
said ninth mux having a 0-input connected to said eighth one of said input terminals, an inverting 1-input connected to said output of said first mux, a select control connected to said first control terminal, and an output.

9 more elements

Dependencies are inferred from the claim text.

Field programmable gate array logic module configurable as combinational or sequential circuits

Life of this patent

Field programmable gate array logic module configurable as combinational or sequential circuits

Life of this patent

Abstract

Claims19