Output buffer circuit having a minimized output voltage propagation
AssigneeNEC Corporation
InventorYasuhiro Ohnishi
Life of this patent
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Abstract
In an output buffer circuit so configured that a capacitor connected to a gate of an output driving MOS transistor and including a gate capacitance of the output driving MOS transistor is gradually charged through a resistor, so as to realize a slow rising or falling time, there is additionally provided a threshold voltage charging circuit for rapidly charging the capacitor to a threshold voltage level of the output driving MOS transistor when the output driving MOS transistor is to be turned on. With this arrangement, the propagation delay time of an output voltage can be minimized.
Claims4
An output buffer circuit comprising:
- an input terminal;
- an output terminal;
- an output driving P-channel transistor having a drain electrode connected to said output terminal and a source electrode connected to a voltage supply line;
- a capacitor having one end connected to a gate electrode of said output driving P-channel transistor, the other end of said capacitor being connected to said voltage supply line;
- an inverter having an input connected to said input terminal and an output connected through a resistor to said one end of said capacitor;
- a discharging P-channel transistor having a gate connected to said input terminal and connected in parallel to said capacitor, so that when a potential on said input terminal is brought to a low level for the purpose of turning off said output driving P-channel transistor, said discharging P-channel transistor is turned on so as to discharge said capacitor;
- and
- a threshold voltage charging circuit connected to said one end of said capacitor and controlled by said potential on said input terminal for rapidly charging said capacitor to a threshold voltage level of said output driving P-channel transistor when the potential on said input terminal is brought to a high level for the purpose of turning on said output driving P-channel transistor.
An output buffer circuit comprising:
- an input terminal;
- an output terminal;
- an output driving N-channel transistor having a drain electrode connected to said output terminal and a source electrode connected to a ground line;
- a capacitor having one end connected to a gate electrode of said output driving N-channel transistor, the other end of said capacitor being connected to said ground line;
- an inverter having an input connected to said input terminal and an output connected through a resistor to said one end of said capacitor;
- a discharging N-channel transistor having a gate connected to said input terminal and connected in parallel to said capacitor, so that when a potential on said input terminal is brought to a high level for the purpose of turning off said output driving N-channel transistor, said discharging N-channel transistor is turned on so as to discharge said capacitor;
- and
- a threshold voltage charging circuit connected to said one end of said capacitor and controlled by said potential on said input terminal for rapidly charging said capacitor to a threshold voltage level of said output driving N-channel transistor when the potential on said input terminal is brought to a low level for the purpose of turning on said output driving N-channel transistor.
Dependencies are inferred from the claim text.