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US 5,633,534 AGranted
Integrated circuit with enhanced planarization
AssigneeSGS-Thomson Microelectronics S.A.
InventorsAlex Kalnitsky, Yih-Shung Lin
Life of this patent
Estimating the term…
Abstract
A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.
Claims24
An integrated circuit manufactured by a method comprising the steps of:
- (a.) providing a partially fabricated integrated circuit structure which has an uneven topography;
- (b.) applying and curing spin-on glass, to form a first planarizing dielectric layer;
- (c.) depositing dielectric material from the vapor phase, to form a second dielectric layer directly over said first layer;
- (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer directly over said first and second layers;
- (e.) substantially removing said dielectric stack from high points of said partially fabricated structure while leaving said dielectric stack in other portions of said partially fabricated structure;
- (f.) deposition of an interlevel dielectric;
- (g.) etching holes in said interlevel dielectric in predetermined locations;
- and
- (h.) depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
6 more elements
An integrated circuit manufactured by a method comprising the steps of:
- (a.) providing a partially fabricated integrated circuit structure;
- (b.) applying and curing spin-on glass, to form a first planarizing dielectric layer;
- (c.) depositing silicon dioxide from the vapor phase, to form a second dielectric layer directly over said first layer;
- (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer directly over said first and second layers;
- (e.) substantially removing said dielectric stack from high points of said partially fabricated structure while leaving said dielectric stack in other portions of said partially fabricated structure;
- (f.) deposition of an interlevel dielectric;
- (g.) etching holes in said interlevel dielectric in predetermined locations;
- and
- (h.) depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
6 more elements
An integrated circuit manufactured by a method comprising the steps of:
- (a.) providing a partially fabricated integrated circuit structure;
- (b.) applying and curing spin-on glass, to form a first planarizing dielectric layer;
- (c.) depositing dielectric material from the vapor phase, to form a second dielectric layer directly over said first layer, said second dielectric layer having a thickness equal to or less than said first layer;
- (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer directly over said first and second layers, said third dielectric layer having a thickness equal to or greater than said second layer;
- (e.) substantially removing said dielectric stack from high points of said partially fabricated structure while leaving said dielectric stack in other portions of said partially fabricated structure;
- (f.) deposition of an interlevel dielectric;
- (g.) etching holes in said interlevel dielectric in predetermined locations;
- and
- (h.) depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
6 more elements
An integrated circuit, comprising:
- (a.) an active device structure, including therein a substrate, active device structures, isolation structures, and one or more patterned thin film conductor layers including an uppermost conductor layer;
- and
- (b.) a planarization structure, overlying recessed portions of said active device structure, comprising a layer of sol-gel-deposited planarizing dielectric directly overlain by a layer of vapor-phase-deposited dielectric directly overlain by a further layer of sol-gel-deposited planarizing dielectric, without any intervening conductor layers;
- (c.) an interlevel dielectric overlying said planarization structure and said active device structure, and having via holes therein which extend to selected locations of said uppermost conductor layer;
- and
- (d.) an additional thin-film patterned conductor layer which overlies said interlevel dielectric and extends through said via holes to said selected locations of said uppermost conductor layer.
3 more elements
An integrated circuit fabricated by a method comprising the steps of:
- (a.) providing a partially fabricated integrated circuit structure which has an uneven topography;
- (b.) applying and curing spin-on glass, to form a first planarizing dielectric layer;
- (c.) depositing dielectric material from the vapor phase, to form a second dielectric layer directly over said first layer;
- (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer directly over said first and second layers;
- (e.) substantially removing said dielectric stack from high points of said partially fabricated structure while leaving said dielectric stack in other portions of said partially fabricated structure;
- (f.) etching holes in said dielectric stack in predetermined locations;
- and
- (g.) depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
5 more elements
An integrated circuit fabricated by a method comprising the steps of:
- (a.) providing a partially fabricated integrated circuit structure which has an uneven topography;
- (b.) applying and curing spin-on glass, to form a first planarizing dielectric layer;
- (c.) depositing dielectric material from the vapor phase, to form a second dielectric layer directly over said first layer;
- (d.) applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer directly over said first and second layers;
- (e.) deposition of an interlevel dielectric;
- (f.) etching holes in said interlevel dielectric and said dielectric stack in predetermined locations;
- and
- (g.) depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
5 more elements
Dependencies are inferred from the claim text.