Gate array semiconductor integrated circuit device

A gate array semiconductor integrated device, comprising:

• an insulating layer;
• a semiconductor layer being formed on an upper major surface of said insulating layer;
• N-type and P-type MOS transistors, having gate electrodes in gate length directions and gate width directions corresponding to a first direction and a second direction being perpendicular to said first direction respectively, being adjacently formed in said semiconductor layer and on its upper major surface through an isolation region;
• said isolation region comprising:
• a P-type isolation region layer being formed in said semiconductor layer along said first direction;
• an N-type isolation region layer being formed in said semiconductor layer along said first direction;
• and
• a field oxide film being formed between one end surface of said P-type isolation region layer and one end surface of said N-type isolation region layer,
• a P-type extended layer being formed in said semiconductor layer, said P-type extended layer having one end surface being bonded to one end surface being perpendicular to said second direction of a channel region of said N-type MOS transistor and another end surface being bonded to another end surface being perpendicular to said second direction of said P-type isolation region layer;
• an N-type extended layer being formed in said semiconductor layer, said N-type extended layer having one end surface being bonded to one end surface being perpendicular to said second direction of a channel region of said P-type MOS transistor and another end surface being bonded to another end surface being perpendicular to said second direction of said N-type isolation region layer;
• a first oxide film covering said semiconductor layer, said isolation region and said N-type and P-type MOS transistors;
• a first subsource line being formed on an upper major surface of said first oxide film along said first direction and being at a source potential;
• a second subsource line being formed on said upper major surface of said first oxide film along said first direction and being at a potential being lower than said source potential;
• a third subsource line being formed on a portion of said upper major surface of said first oxide film and being just above said P-type isolation region layer along said first direction;
• a fourth subsource line being formed on a portion of said upper major surface of said first oxide film and being just above said N-type isolation region layer along said first direction;
• a second oxide film covering respective said first to fourth subsource lines;
• a first main source line being positioned above said fourth subsource line and formed on an upper major surface of said second oxide film along said second direction with a line width being set to be larger than those of said first and second subsource lines, said first main source line being at said source potential;
• and
• a second main source line being positioned above said third subsource line and formed on said upper major surface of said second oxide film along said second direction with a line width being set to be larger than those of said first and second subsource lines, said second main source line being at a potential being lower than said source potential,
• said P-type isolation region layer and said third subsource line being connected with each other through a contact portion being provided in said first oxide film,
• said N-type isolation region layer and said fourth subsource line being connected with each other through another contact portion being provided in said first oxide film,
• said first main source line and said first subsource line being connected with each other through a first contact portion being provided in said second oxide film,
• said second main source line and said second subsource line being connected with each other through a second contact portion being provided in said second oxide film,
• said second main source line and said third subsource line being connected with each other through a third contact portion being provided in said second oxide film,
• said first main source line and said fourth subsource line being connected with each other through a fourth contact portion being provided in said second oxide film.

A gate array semiconductor integrated circuit device, comprising:

• an insulating layer;
• a semiconductor layer being formed on an upper major surface of said insulating layer;
• N-type and P-type MOS transistors being formed in said semiconductor layer and on its upper major surface;
• and
• a gate circuit portion including said N-type and P-type MOS transistors and operating through operating power sources of a first source potential and a second source potential being lower than said first source potential, wherein
• a back gate potential of either said N-type or P-type MOS transistor is set at a potential being lower than said first source potential and higher than said second source potential.

A gate array semiconductor integrated circuit device, comprising:

• an insulating layer;
• a semiconductor layer being formed on an upper major surface of said insulating layer;
• N-type and P-type MOS transistors being formed in said semiconductor layer and on its upper major surface;
• and
• a gate circuit portion including said N-type and P-type MOS transistors and operating through operating power sources of a first source potential and a second source potential being lower than said first source potential, wherein
• a back gate potential of said P-type MOS transistor is set at a third potential being lower than said first source potential and higher than said second source potential, and
• a back gate potential of said N-type MOS transistor is set at a fourth potential being lower than said first source potential and higher than said second source potential.

A gate array semiconductor integrated circuit device, comprising:

• an insulating layer;
• a semiconductor layer being formed on an upper major surface of said insulating layer;
• a first source wiring layer, being at a first source potential, being formed on an upper major surface of said semiconductor layer;
• a second source wiring layer, being at a second potential being lower than said first source potential, being formed on said upper major surface of said semiconductor layer;
• N-type and P-type MOS transistors, having gate electrodes in gate length directions and gate width directions corresponding to a first direction and a second direction being perpendicular to said first direction respectively, being adjacently formed in said semiconductor layer and on its upper major surface through an isolation region;
• said isolation region being formed in said semiconductor layer along said first direction,
• a P-type extended layer being formed in said semiconductor layer along said first direction, said P-type extended layer having one end surface being bonded to one end surface being perpendicular to said second direction of a channel region of said N-type MOS transistor and another end surface being bonded to one end surface being perpendicular to said second direction of said isolation region;
• another P-type extended layer being formed in said semiconductor layer, said another P-type extended layer having one end surface being bonded to another end surface being perpendicular to said second direction of said channel region of said N-type MOS transistor and an upper major surface being connected with said second source wiring layer;
• an N-type extended layer being formed in said semiconductor layer along said first direction, said N-type extended layer having one end surface being bonded to one end surface being perpendicular to said second direction of a channel region of said P-type MOS transistor and another end surface being bonded to another end surface being perpendicular to said second direction of said isolation region;
• another N-type extended layer being formed in said semiconductor layer, said another N-type extended layer having one end surface being bonded to another end surface being perpendicular to said second direction of said channel region of said P-type MOS transistor and an upper major surface being connected with said first source wiring layer;
• and
• an end cell region having an end cell corresponding to a basic cell consisting of said N-type and P-type MOS transistors, said end cell region being formed on each end of a region being formed by repeatedly arranging said basic cell in said first direction while symmetrically arranging the same to be folded in said second direction, wherein
• all of said P-type extended layer, said another P-type extended layer, said N-type extended layer and said another N-type extended layer are extended in said semiconductor layer along said first direction to reach said end cell region,
• a part of said isolation region being formed along said first direction also defines a part of said end cell,
• said end cell comprises:
• an end cell P-type semiconductor layer being formed in said semiconductor layer along said second direction so that one of end surfaces thereof being perpendicular to said second direction is bonded to one end surface of said part of said isolation region;
• and
• an end cell N-type semiconductor layer being formed in said semiconductor layer along said second direction so that one of end surfaces thereof being perpendicular to said second direction is bonded to another end surface of said part of said isolation region,
• one and another end portions of said end cell P-type semiconductor layer are connected to said P-type extended layer and said another P-type extended layer respectively, and
• one and another end portions of said end cell N-type semiconductor layer are connected to said N-type extended layer and said another N-type extended layer respectively.