US 5,633,522 A · CMOS transistor with two-layer inverse-T tungsten gate

Abstract

The present invention is directed to a unique silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted "T". A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

Claims12

Dependent claims

An MOS transistor with an inverted-T refractory metal gate, comprising in combination:

a semiconductor substrate;
a gate insulating layer on said semiconductor substrate;
a first refractory metal layer formed on said insulating gate layer comprising a material formed to have a low density relative to the density of a second refractory metal layer;
said second refractory metal layer formed on said first refractory metal layer comprising said material formed to have a high density relative to said low density of said first refractory metal layer;
said first refractory metal layer extending laterally beyond said second refractory metal layer;
and
a source and drain region in said semiconductor substrate extending under said first refractory metal layer,
wherein said first refractory metal layer and said second refractory metal layer comprise a same material.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

08/648,457Filed 15 May 1996 · continuation

Priority

18 Jun 1992

Granted

27 May 1997

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 64/01316
Characterised by the conductor: the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
H10D 64/01324
Characterised by the conductor: characterised by the sectional shape, e.g. T or inverted-T
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers

CMOS transistor with two-layer inverse-T tungsten gate

Life of this patent

CMOS transistor with two-layer inverse-T tungsten gate

Life of this patent

Abstract

Claims12