Enhancement of breakdown voltage in MOSFET semiconductor device

A MOSFET semiconductor device comprising a p-type substrate,

• said p-type substrate including:
• an n-type drain region;
• an n.sup.- -type drain region located adjacent to said n-type drain region;
• an n+-type drain layer located within said n-type drain region and at a surface of said p-type substrate;
• a p-type top layer located adjacent to said n.sup.- -type drain region and at a surface of said p-type substrate;
• an n+-type source region;
• and
• a p+-type back gate,
• a layout pattern constituted of said regions and layers including at least a pair of said regions and layers having elongated portions substantially parallel to each other and which change direction along said surface so as to form a curved portion,
• said n.sup.- -type drain region covering therein said p-type top layer therewith in an area proximate to said curved portions of said layout pattern,
• said n-type drain region being formed so that said n-type drain region overlaps said p-type top layer in said elongated portions of said layout pattern and does not overlap said p-type top layer in said area proximate to said curved portions of said layout pattern.