Semiconductor wafer incorporating marks for inspecting first layer overlay shift in global alignment process

Abstract

An inspection pattern on a semiconductor wafer for inspecting is used to determine the degree of alignment of a first device layer during manufacture of integrated circuits on a semiconductor substrate the following steps. Form a zeroth layer on the substrate. The alignment marks and zeroth layer mother overlay inspection patterns are patterned simultaneously in the zeroth layer aligning to alignment marks formed in the zeroth layer. Then one forms a first layer on the substrate patterned simultaneously with formation of child overlay inspection patterns patterned in the sake position as the zeroth layer mother inspection patterns to determine the overlay shift of the first layer.

Dependencies are inferred from the claim text.