Method of making a non-volatile memory cell

A method for fabricating an array of floating gate memory devices on a substrate, comprising:

• forming a plurality of insulating regions on the substrate elongated in a first direction and spaced apart to define a plurality of isolated regions in the substrate elongated in the first direction;
• depositing a first insulating material on the substrate at least in elongated channel regions within isolated regions in the substrate;
• depositing a floating gate conductive material over the first insulating material at least in the elongated channel regions;
• depositing a control gate insulating material over the floating gate conductive material;
• selectively removing the floating gate conductive material and control gate insulating material in a pattern to form a plurality of lines and to expose elongated source diffusion regions and drain diffusion regions in the substrate, extending along the substrate between the lines in the plurality of lines, aligned on at least one side with the floating gate conductive material and at least one of the source diffusion regions or the drain diffusion regions aligned with the insulating regions on the other side, the drain diffusion regions extending at one end past the source diffusion regions in one direction, the drain diffusion regions being widened at the one end to form a drain of a first set of select transistors, the source diffusion regions being formed to couple to a second plurality of drain diffusion regions, the second plurality of drain diffusion regions being elongated in a direction substantially orthogonal to the direction of the plurality of lines, the second drain diffusion regions to form the drains of a second set of select transistors, each second drain diffusion region being coupled to at least two of said second source diffusion regions;
• doping the source and drain diffusion and second drain diffusion regions;
• growing an insulating layer over the source and drain diffusion regions and exposed portions of said floating gate conductive material on sides of the lines;
• establishing a control gate conductive material over the control gate insulating material and the insulating layer;
• and
• removing the control gate conductive material, and portions of the lines of control gate insulating material and the floating gate conductive material in a pattern to form wordlines over the substrate and substantially perpendicular to the elongated source and drain diffusion regions, and to form floating gates under the wordlines, so that a plurality of columns of contactless floating gate transistors is formed, and the drains of the contactless floating gate transistors in each column are formed in one of the drain diffusion regions and the sources of the contactless floating gate transistors in each column are formed in one of the source diffusion regions.