Method of making semiconductor device with floating bate
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKatsuhiko Tamura, Yukari Imai, Naoko Otani
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Abstract
A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.
Claims20
A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of:
- forming a first insulating layer having a first thickness and formed at least on that region of said main surface of said semiconductor substrate on which said channel region is formed;
- forming a second insulating layer having a second thickness larger than said first thickness at least on a region, on which one of said impurity regions is formed, of said main surface of said semiconductor substrate;
- forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer;
- forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween;
- patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode;
- and
- implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.
A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of:
- forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed;
- forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate;
- forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer;
- forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween;
- patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode;
- and
- implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.
A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of:
- forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate;
- forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being of a different material than said first insulating layer;
- forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer;
- forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween;
- patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode;
- and
- implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.
A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of:
- forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate;
- forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer;
- forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer;
- forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween;
- patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode;
- and
- implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.
A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of:
- forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate;
- forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being of a different material than said first insulating layer;
- forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer;
- forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween;
- patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode;
- and
- implanting impurity into said semiconductor substrate only after said step of patterning said control electrode layer, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.
A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of:
- forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed;
- forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate;
- forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer;
- forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being of a different material than said first insulating layer;
- patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode;
- and
- implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.
A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of:
- forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed;
- forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate;
- forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer;
- forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer;
- patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode;
- and
- implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.
A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of:
- forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed;
- forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate;
- forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer;
- forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer;
- patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode;
- and
- implanting impurity into said semiconductor substrate only after said step of patterning said control electrode layer, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.
Dependencies are inferred from the claim text.