FET having minimized parasitic gate capacitance

A method for fabricating a field effect transistor, having minimal parasitic gate capacitance, comprising:

• forming a buffer layer having a pulse doped layer inserted into said buffer layer, on a substrate;
• forming a channel layer having first and second areas, on said buffer layer, wherein the first area has an active region for a source, gate and drain;
• forming a gate insulator on said channel layer;
• forming a first layer of gate metal on said gate insulator layer, wherein said first layer of gate metal is transparent to ion implanting;
• forming a photoresist layer on said first layer of gate metal, over the first area of the channel layer, where said photoresist layer prevents ion implanting;
• ion implanting through a portion of said first layer of gate metal, gate insulator layer and channel layer, thereby resulting in the second area of the channel layer being non conducting;
• removing said photoresist layer;
• forming a second gate metal layer on said first gate metal layer;
• patterning said first and second gate metal layers into a metal gate pad or interconnect over the second area of the channel layer and at least one gate finger over the first area of the channel layer;
• and
• etching portions of said first and second gate metal layers so as to leave the metal gate pad or interconnect over the second area of the channel layer and at least one metal gate finger over the first area of the channel layer of said wafer.