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US 5,633,178 AGranted
Method of making volatile memory cell with interface charge traps
AssigneeSGS-Thomson Microelectronics S.A.
InventorAlexander Kalnitsky
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Abstract
A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.
Claims8
A method of manufacturing a volatile memory cell including the steps of:
- forming a layer of silicon dioxide on a p-type monocrystalline silicon substrate;
- covering the silicon dioxide layer with a layer of conductive material and forming a gate electrode of the volatile memory cell;
- and
- implanting silicon ions into the silicon dioxide layer so that substantially all of said ions in the silicon dioxide layer are located within approximately 1.0 nm of an interface between the silicon dioxide layer and the silicon substrate.
1 more element
A method of manufacturing a memory cell including the steps of:
- forming an insulating layer on a semiconductor layer;
- forming a conducting layer on the insulating layer, said conducting layer forming a gate electrode, and
- implanting silicon ions into the insulating layer so that substantially all of said ions in the insulating layer are located within approximately 1.0 nm of an interface between the insulating layer and the semiconductor layer.
Dependencies are inferred from the claim text.