Test fixture and method for producing a test fixture for testing unpackaged semiconductor die

A method for forming a test fixture for testing an unpackaged semiconductor die, comprising:

• forming a base;
• forming a contact structure on the base, said contact structure configured to electrically contact a contact location on the die;
• forming an electrical path between the contact structure and test circuitry;
• forming an alignment member on the base comprising an alignment opening configured to form a sealed space between the die and base;
• forming a vacuum opening on the base to the sealed space;
• and
• applying a vacuum through the vacuum opening to the sealed space to press the die against the base with the contact structure on the base in electrical contact with the contact location on the die.

A method for forming a test fixture for testing a semiconductor die, comprising:

• forming an unpackaged base;
• forming a contact structure on the base, configured to establish electrical communication between a bond pad on the die and test circuitry;
• forming an alignment layer on the base with an alignment opening therein configured to seal around a periphery of the die to form a sealed space;
• forming a vacuum opening through the base to the alignment opening;
• and
• applying a vacuum through the opening to the space to press the die against the base with the contact structure on the base in electrical contact with the bond pad on the die.

A test fixture for testing an unpackaged semiconductor die comprising:

• a base having an opening thereon in flow communication with a vacuum source;
• a contact structure formed on the base for establishing temporary electrical communication between a contact location on the die and test circuitry;
• and
• an alignment member formed on the base for aligning the contact structure and contact location, said alignment member comprising an alignment opening configured to contact an outer periphery of the die and form a sealed space in flow communication with the opening for applying a vacuum pressure to the die.

A method for testing an unpackaged semiconductor die comprising:

• providing a base having an opening thereon in flow communication with a vacuum source;
• providing a contact structure on the base in electrical communication with test circuitry and configured to establish temporary electrical communication with a contact location on the die;
• providing an alignment member on the base comprising an alignment opening configured to contact an outer periphery of the die to form a space in flow communication with the opening;
• aligning the die with the base using the alignment member;
• and
• applying a vacuum pressure through the opening to the space to press the die against the base with the contact structure and contact location in temporary electrical communication.