Microprocessor having power management circuitry with coprocessor support
AssigneeCyrix Corporation
InventorsRobert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
Life of this patent
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Abstract
A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detecting circuitry detects the assertion of a first signal indicative of a request for suspending operation of the processing unit and the assertion of a second signal indicating the state of operation of a coprocessing unit. Disabling circuitry is operable to disable clock signals to one or more of the subcircuits responsive to the first and second control signals.
Claims8
A microprocessor having power management circuitry with coprocessor support, comprising:
- (a) clock generation means for supplying a first and a second clock signal;
- (b) core means, coupled to the clock generation means to receive the first clock signal, for executing instructions;
- (c) memory management means, coupled to the clock generation means to receive the first clock signal, for managing memory access;
- and,
- (d) bus controller means, coupled to the clock generation means to receive the second clock signal, and to an external source to receive a suspend request signal, and to a coprocessor to receive a busy signal, for disabling the first clock signal in response to the suspend request signal being asserted and the busy signal being de-asserted.
A computer system employing a microprocessor having power management circuitry with coprocessor support, comprising:
- (a) a memory;
- (b) a BIOS ROM;
- (c) chipset logic providing a suspend request signal;
- (d) a coprocessor providing a busy signal;
- and
- (e) a microprocessor including clock circuitry, core circuitry, memory management circuitry, and bus control circuitry, coupled to the memory, the BIOS ROM, the chipset logic, and the coprocessor to receive signals therefrom,
- the clock circuitry being coupled to the core circuitry, the memory management circuitry, and the bus control circuitry,
- the bus control circuitry having inputs coupled to the suspend request signal and the busy signal,
- in response to the suspend request signal being asserted and the busy signal being de-asserted, the bus control circuitry disabling the clock circuitry to the core circuitry and the memory management circuitry so that power consumption in the microprocessor is reduced.
In a computer system having a coprocessor and a microprocessor including clock circuitry, core circuitry, memory management circuitry, and bus control circuitry, a method of power management comprising the steps of:
- (a) receiving a request from an external source to suspend the clock circuitry into the bus control circuitry;
- (b) checking that a busy signal received from the coprocessor is de-asserted;
- and,
- (c) suspending the clock circuitry to the core circuitry and memory management circuitry in response to steps (a) and (b).
Dependencies are inferred from the claim text.