Method for preventing multi-level cache system deadlock in a multi-processor system

A method of controlling the execution of cache memory access instructions in a computer system comprising a plurality of processing units each having at least one cache, wherein multi-processor cache coherency is maintained in the computer system, at least one of the processing units including a split-level cache arrangement comprising a first level cache coupled to a second level cache, the first level cache being byte writable and the second level cache being word writable, the split-level cache arrangement supporting an integer store operation which causes data to be stored in both the first level cache and the second level cache, wherein during execution of an integer store operation one or more bytes are read from the first level cache and written to the second level cache along with write data of the integer store operation such that data of word length is written to the second level cache as a result of the integer store operation, such execution of an integer store operation being performed atomically, the method comprising the steps of:

• (a) determining whether an aligned multi-byte word in which the write data of an integer store operation is contained is exclusive in the first level cache;
• and
• (b) if it is determined that the aligned word is not exclusive in the first level cache, then preventing the integer store operation from entering a pipeline of the second level cache, and initiating a cache miss and fill operation to cause the aligned word to be exclusive in the first level cache,
• wherein interventions to the second level cache are not permitted while an integer store operation is in the second level cache pipeline.