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US 5,632,024 AGranted
Microcomputer executing compressed program and generating compressed branch addresses
AssigneeHitachi, Ltd.
InventorsHiroshi Yajima, Yugo Kashiwagi
Life of this patent
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Abstract
An executable program is stored in compressed form in a ROM, from which compressed program data is fetched to be expanded by an expandor to a pre-compression form. The expanded data is then decoded by an instruction decoder for execution. This novel setup reduces a memory usage amount in main storage including the ROM. If a branch instruction appears, a controller converts a pre-compression branch destination address to a corresponding post-compression branch destination address and sets a value thereof to a program counter.
Claims27
A method of executing compressed program data in a microcomputer, the compressed program data provided by compressing a program having a plurality of instructions and stored in a memory, the compressed program data addressable by a plurality of addresses, comprising the steps of:
- fetching data from a predetermined address in said compressed program data stored in the memory, wherein the predetermined address is provided by a program counter;
- expanding said fetched data;
- decoding said expanded data;
- determining whether the decoding indicates a change in compressed program execution sequence;
- executing an operation in accordance with the result of said decoding;
- generating an address for said compressed data program indicating the next data of said compressed data program to be fetched by incrementing the predetermined address if the decoding does not indicate a change in the compressed program execution sequence;
- and
- generating a branch address for said compressed data program to indicate a destination address in said compressed data program by extracting a compressed branch address from a compressed address translation table if the decoding indicates a change in the compressed program execution sequence.
5 more elements
A microcomputer comprising:
- program counter means for indicating an instruction address;
- storage means for storing compressed program data provided by compressing a program having a plurality of instructions, said storage means being connected to said program counter means;
- expanding means including means for fetching data from the instruction address indicated by said program counter means and means for expanding the fetched data;
- decoding means for decoding the expanded data from said expanding means;
- execution means for executing operations in response to the decoding of the expanded data by the decoding means;
- execution sequence determining means coupled to said decoding means for determining whether the decoding by said decoding means indicates a change in instruction execution sequence;
- address generation means including a compressed address translation table for generating a branch address indicating a destination address within said compressed program data by extracting a compressed branch address corresponding to the branch address included in said fetched data from the compressed address translation table;
- and
- setting means for setting the address generated by said address generation means in said program counter means in response to an indication of a change in the instruction execution sequence, and for incrementing the instruction address in said program counter means in response to an indication of no change in the instruction execution sequence.
6 more elements
In a microcomputer for use with a memory which stores a compressed program which has been provided by compressing a program having a plurality of instructions, the microcomputer comprising:
- a program counter generating an address by an increment operation, the generated address indicating an address of the compressed program;
- a data expander expanding data of the compressed program indicated by the address generated by the program counter;
- an instruction decoder decoding the expanded data and generating an output;
- an execution unit executing an operation in accordance with the output of the instruction decoder;
- an instruction determination unit, responsive to the output of the instruction decoder, determining whether the operation to be executed by the execution unit includes a branch operation;
- an address generation unit including a compressed address translation table and generating destination address data for indicating a destination in the compressed program by extracting compressed branch address data from the compressed address translation table if the instruction determination unit has determined that the operation to be executed by the execution unit includes the branch operation;
- and
- a setting unit setting the generated destination address data to the program counter if the instruction determination unit has determined that the operation to be executed by the execution unit includes a branch operation,
- wherein data from the destination in the compressed program indicated by the destination address data is expanded by the data expander and executed by the execution unit.
6 more elements
A microcomputer executing a compressed program of instructions addressable by addresses, the instructions of the compressed program addressable by addresses, the compressed program generated by compressing an initial program of instructions, comprising:
- a program counter storing an address indicating an instruction of the compressed program;
- a memory storing instructions of the compressed program;
- an instruction expander coupled to the memory, the instruction expander sequentially receiving and selectively expanding the instructions of the compressed program and generating instructions corresponding to the initial program;
- an instruction decoder decoding instructions from the instruction expander and generating an output;
- an execution unit executing the instructions from the instruction expander in response to the instruction decoder output;
- an address translator including a compressed address translation table and generating the compressed branch addresses indicating addresses in the compressed program by extracting a compressed branch from the compressed address translation table, wherein, in response to an output which is provided from the instruction decoder and which indicates a change in sequence of the compressed program, the address translator stores in the program counter the compressed branch address in the compressed program so that an instruction at the address indicated by the compressed branch address can be executed in response to the change in sequence of the compressed program.
3 more elements
In a microcomputer for use with a memory which stores a program which has been compressed, the microcomputer comprising:
- a program counter generating an address of the compressed program;
- a data expander selectively expanding data of the compressed program indicated by the address generated by the program counter;
- an instruction decoder decoding the expanded data and generating an output;
- an execution unit executing an operation in accordance with the output of the instruction decoder;
- an instruction determination unit responsive to the output of the instruction decoder, determining whether the operation to be executed by the execution unit includes a branch operation;
- an address generation unit generating compressed destination address data indicating a destination in the compressed program if the instruction determination unit has determined that the operation to be executed by the execution unit includes a branch operation, wherein the address generation unit includes:
- a compressed address translation table including a plurality of destination data indicating destination addresses for branch operations in the program before being compressed and a plurality of compressed destination address data which correspond to the plurality of destination data and which indicate compressed destination addresses in the compressed program;
- and
- an address table search unit which searches the plurality of destination data to find compressed destination address data if the instruction determination unit has determined that the operation to be executed by the execution unit includes the branch operation;
- and
- a setting unit setting the compressed destination address data to the program counter if the instruction determination unit has determined that the operation to be executed by the execution unit includes a branch operation;
- wherein data indicated by the compressed destination address data in the compressed program is expanded by the data expander and executed by the execution unit.
9 more elements
Dependencies are inferred from the claim text.