Computer system with cascaded peripheral component interconnect (PCI) buses
AssigneeCisco Systems, Inc.
InventorsWilliam E. Jennings, Roland G. Chan, John L. Wong
Life of this patent
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Abstract
A system including primary and secondary PCI (Peripheral Component Interconnect) buses which do not "livelock". The system includes two PCI to PCI bridges between the primary and secondary buses. One of the bridges is configured to only act as a target on the primary bus and as a master on the secondary bus, the second bridge is configured to only act as master on the primary bus and as a target on the secondary bus. The determination of which data path is chosen is not made by the bridges and thus the bridges do not bias the direction of transmissions to one bus or to the other bus.
Claims14
A system including
- a primary Peripheral Component Interconnect (PCI) bus,
- a secondary PCI bus,
- a first PCI to PCI bridge connecting said primary PCI bus to said secondary PCI bus, said first PCI to PCI bridge configured to only respond as a master on said primary bus, and as a target on said secondary bus, and
- a second PCI to PCI bridge connecting said primary PCI bus to said secondary PCI bus, said second PCI to PCI bridge configured to only respond as a master on said secondary bus and as a target on said primary bus,
- whereby said system avoids a livelock situation with respect to transmissions between said primary and said secondary buses.
A system including a host controller,
- a first Peripheral Component Interconnect (PCI) bus connected to said host controller,
- a second PCI bus,
- a third PCI bus,
- a first and a second PCI bridge circuit connecting said first PCI bus to said second PCI bus,
- said first PCI bridge configured to act as a master only on said first PCI bus and said second PCI bridge configured to act as a master only on said second PCI bus, and
- third and fourth PCI bridge circuits connecting said first PCI bus to said third PCI bus, said third PCI bridge configured to act as a master only on said first PCI bus and said fourth PCI bridge configured to act as a master only said third PCI bus,
- whereby a livelock situation is avoided relative to transmissions between said buses.
A system including
- a first bus,
- a second bus,
- a bridge connecting said first bus to said second bus, said first bus configured to only respond as a master on said first bus, and as a target on said second bus, and
- a second bridge connecting said first bus to said second bus, said second bridge configured to only respond as a master on said second bus and as a target on said first bus,
- whereby said system avoids a livelock situation with respect to transmissions between said first and said second buses.
Dependencies are inferred from the claim text.