Circuit and method of encrypting key validation

An integrated circuit for encrypting a key validation, comprising:

• a first register coupled for receiving data and a select offset and a seed offset where said select offset identifies a polynomial select code within said data and said seed offset identifies a polynomial seed within said data;
• a select decode logic circuit coupled for receiving said polynomial select code for providing a polynomial;
• a polynomial generator coupled for receiving said polynomial from said select decode logic circuit and further coupled for receiving said polynomial seed for defining a starting point of said polynomial, said polynomial generator being clocked a first number of cycles to calculate a remainder in said polynomial generator;
• and
• a modification circuit having a first input coupled for receiving said polynomial select, and an output for providing an updated polynomial select code to said select decode logic circuit.

A method of encrypting a validation sequence in an integrated circuit between a key and a host, comprising the steps of:

• receiving data from a host where said data includes a 5 first polynomial select code and a polynomial seed;
• decoding said first polynomial select code into a first polynomial;
• configuring a polynomial generator with said first polynomial;
• loading said polynomial generator with said polynomial seed as a starting point of said first polynomial;
• clocking said polynomial generator a first number of cycles based on a first clock count from said starting point to calculate a first remainder in said polynomial generator;
• configuring said polynomial generator with a second polynomial;
• and
• clocking said polynomial generator a second number of cycles based on a second clock count from said first remainder to calculate a second remainder in said polynomial generator.