US 5,631,960 A · Autotest of encryption algorithms in embedded secure encryption devices

Abstract

An internal state machine controller in an integrated circuit containing a cryptographic implementation independently tests and verifies each of the encryption and decryption algorithms and modes within the implementation with minimal processor intervention. The cryptographic implementation automatically generates all input data and exercises all feedback modes independent of the core processor. Eliminating external test vectors results in a device less expensive to manufacture and verify. Since the cryptographic implementation tests are performed independent of the processor, other parts of the integrated circuit may be tested simultaneously with the testing of the cryptographic implementation. The processor loads in a single set of predetermined test vectors and then signals the state machine to start the testing of all the algorithms contained in the module. The output of each algorithm is used as the input of the next algorithm. The encrypted output from each algorithm is then fed back into the algorithms in reverse order and decrypted. At the end of this cycle the data returned should match the original data exactly. This is considered a cycle. The number of cycles is programmable depending on the test requirements and or fault coverage desired. In the preferred embodiment, the cryptographic implementation includes a cryptographic engine having encryption and decryption modes. Output Feedback (OFB), Electronic Codebook (ECB), Cipher Block Chaining (CBC), and Cipher Feedback (CFB) modes are supported in the preferred embodiment of the present invention.

Claims22

Dependent claims

A method of testing a cryptographic accelerator that implements a cryptographic function having a state that is either an encryption state or a decryption state, such that the encryption state is an inverse decryption state, and such that the decryption state is an inverse encryption state, implementing the cryptographic function in each of n modes, comprising the steps of:

for integer i equal 1,
performing a first cryptographic operation in a first state in a first mode taking a B-bit cryptographic test block as input and producing a B-bit first intermediate encrypted result;
for i from 2 to n,
performing an i.sup.th cryptographic operation in an i.sup.th state in an i.sup.th mode taking the B-bit (i-1).sup.th intermediate result as input and producing a B-bit i.sup.th intermediate encrypted result;
for i from n+1 to 2n-1,
performing an i.sup.th cryptographic operation in the inverse (2n-i+1).sup.th state in the (2n-i +1).sup.th mode taking the B-bit (i-1).sup.th intermediate result as input and producing a B-bit i.sup.th intermediate encrypted result;
and
for i equal 2n,
performing a 2n.sup.th cryptographic operation in the inverse first state in the first mode taking the B-bit (i-1).sup.th intermediate result as input and producing a B-bit accelerator computed test result.

6 more elements

for integer t equal 1,
for integer i equal 1,
performing a first first cryptographic operation in a first first state in a first first mode taking a B-bit cryptographic test block and a first B-bit initial value as inputs and producing a first B-bit first intermediate encrypted result;
for i from 2 to n,
performing a first i.sup.th cryptographic operation in a first i.sup.th state in a first i.sup.th mode taking the first B-bit (i-1).sup.th intermediate result and a first B-bit initial value as inputs and producing a first B-bit i.sup.th intermediate encrypted result;
for i from n+1 to 2n-1,
performing a first i.sup.th cryptographic operation in the inverse first (2n-i+1).sup.th state in the first (2n-i+1).sup.th mode taking the first B-bit (i-1).sup.th intermediate result and a first B-bit initial value as inputs and producing a first B-bit i.sup.th intermediate encrypted result;
and
for i equal 2n,
performing a first 2n.sup.th cryptographic operation in the inverse first first state in the first first mode taking the first B-bit (i-1).sup.th intermediate result and a first B-bit initial value as inputs and producing a first B-bit accelerator computed test result;
updating the first B-bit initial value to create a second B-bit initial value;
for integer t equal 2 to T-1,
for integer i equal 1,
performing a t.sup.th first cryptographic operation in a t.sup.th first state in a t.sup.th first mode taking the (t-1).sup.th B-bit accelerator computed test result and a t.sup.th B-bit initial value as inputs and producing a t.sup.th B-bit first intermediate encrypted result;
for i from 2 to n,
performing an t.sup.th i.sup.th cryptographic operation in an t.sup.th i.sup.th state in an t.sup.th i.sup.th mode taking the t.sup.th B-bit (i-1).sup.th intermediate result and a t.sup.th B-bit initial value as inputs and producing a t.sup.th B-bit i.sup.th intermediate encrypted result;
for i from n+1 to 2n-1,
performing an t.sup.th i.sup.th cryptographic operation in the inverse t.sup.th (2n-i+1).sup.th state in the t.sup.th (2n-i+1).sup.th mode taking the t.sup.th B-bit (i-1).sup.th intermediate result and a t.sup.th B-bit initial value as inputs and producing a t.sup.th B-bit i.sup.th intermediate encrypted result;
and
for i equal 2n,
performing a t.sup.th 2n.sup.th cryptographic operation in the inverse t.sup.th first state in the t.sup.th first mode taking the t.sup.th B-bit(i-1).sup.th intermediate result and a t.sup.th B-bit initial value as inputs and producing a t.sup.th B-bit accelerator computed test result;
updating the t.sup.th B-bit initial value to create a (t+1).sup.th B-bit initial value;
for integer t equal T,
for integer i equal 1,
performing a T.sup.th first cryptographic operation in a T.sup.th first state in a T.sup.th first mode taking the (t-1).sup.th B-bit accelerator computed test result and a T.sup.th B-bit initial value as inputs and producing a T.sup.th B-bit first intermediate encrypted result;
for i from 2 to n,
performing an T.sup.th i.sup.th cryptographic operation in an T.sup.th i.sup.th state in an T.sup.th i.sup.th mode taking the T.sup.th B-bit(i-1).sup.th intermediate result and a T.sup.th B-bit initial value as inputs and producing a T.sup.th B-bit i.sup.th intermediate encrypted result;
for i from n+1 to 2n-1,
performing an T.sup.th i.sup.th cryptographic operation in the inverse T.sup.th (2n-i+1).sup.th state in the T.sup.th (2n-i+1).sup.th mode taking the T.sup.th B-bit(i-1).sup.th intermediate result and a T.sup.th B-bit initial value as inputs and producing a T.sup.th B-bit i.sup.th intermediate encrypted result;
and
for i equal 2n,
performing a T.sup.th 2n.sup.th cryptographic operation in the inverse T.sup.th first state in the T.sup.th first mode taking the T.sup.th B-bit(i-1).sup.th intermediate result and a T.sup.th B-bit initial value as inputs and producing a multi-cycle accelerator computed test result.

29 more elements

Dependencies are inferred from the claim text.

Autotest of encryption algorithms in embedded secure encryption devices

Life of this patent

Autotest of encryption algorithms in embedded secure encryption devices

Life of this patent

Abstract

Claims22