Register circuit

A register circuit comprising a first flip-flop and a second flip-flop,

• said first flip-flop including:
• a first quantizing circuit having a first input terminal for receiving a first analog input voltage and an output terminal for outputting a first quantization of said first analog input voltage according to first predetermined quantizing levels, and
• a switching circuit for alternatively connecting one of said first analog input voltage and an output of said first quantizing circuit to said first input terminal;
• and
• said second flip-flop including:
• a second quantizing circuit having a second input terminal for receiving a second analog input voltage and an output terminal for outputting a second quantization of said second analog input voltage according to second predetermined quantization levels, and
• a switching circuit for alternatively connecting one of an output of said first flip-flop and an output of said second quantizing circuit to said second input terminal;
• and
• wherein, said switching circuits of said first and said second flip-flops are controlled by a clock, timings of said clock for said first flip-flop being reversed from timings of said clock for said second flip-flop.

A register circuit comprising:

• a first flip-flop comprising:
• a first quantizing circuit having a first input terminal for receiving a first analog input voltage and an output terminal for outputting a first quantization of said first analog input voltage according to first predetermined quantization levels, and
• a first switching circuit for selectively connecting one of said first analog input voltage, said first output of said quantizing circuit, a third input and a fourth input to said first input terminal;
• a second flip-flop comprising:
• a second quantizing circuit having a second input terminal for receiving an analog input voltage and a second output terminal for outputting a second quantization of said second analog input voltage according to second predetermined quantization levels, and
• a second switching circuit for selectively connecting one of an output of said first flip-flop and an output of said second quantizing circuit to said second input terminal;
• an increment circuit connected to said output of said second quantizing circuit for outputting a minimum value when said second quantization is a maximum value and otherwise for outputting a value one less than said second quantization as said third input of said first switching circuit;
• and
• a decrement circuit connected to said output of said second quantizing circuit for outputting a maximum value when said second quantization is a minimum value and otherwise for outputting a value one more than said second quantization as said fourth input of said first switching circuit.

A register circuit comprising:

• a quantizing circuit having an input terminal for receiving an analog input voltage and an output terminal for outputting a quantization of said analog input voltage according to predetermined quantizing levels, wherein said quantizing circuit comprises:
• a plurality of thresholding circuits, each thresholding circuit having a common threshold voltage and each having an input terminal and an output terminal, and
• a plurality of capacitive couplings corresponding to said plurality of thresholding circuits, respectively, at least one of said capacitive couplings weighing and adding said analog input voltage to an output of each thresholding circuit having a higher quantizing level;
• a holding circuit for holding said quantized voltage;
• and
• a switching circuit for alternatively connecting at least one of said analog input voltage and an output of said holding circuit to said input terminal of said quantizing circuit.