Bus type clock supplying system for providing a clock in a communication system with a plurality of clock bus lines

A clock supplying system in a communication system within a digital communication network comprising:

• (a) a central processing unit(CPU);
• (b) a clock bus having a plurality of clock lines;
• and
• (c) a plurality of communication cards for transmitting and receiving data through transmission lines within said network, each of said communication cards comprising:
• means for extracting a clock from one of said transmission lines;
• first switching means for connecting said clock extracting means with one of said plurality of clock lines in said clock bus and for breaking connection therebetween;
• selecting means, connected with all of said plurality of clock lines, for selecting a clock line from said plurality of clock lines to receive the clock;
• and
• monitoring and controlling means, connected with said selecting means, said first switching means and said CPU, for monitoring said clock and an input/output signal of said selecting means,
• wherein when where said monitoring and controlling means in any of said communication cards detects abnormalities in the output signal of said selecting means, said monitoring and controlling means informs said CPU thereof and said CPU issues an instruction for controlling said first switching means and said selecting means in all of said communication cards;
• wherein said CPU controls said first switching means of each of said plurality of communication cards such that a single clock is provided to each of the plurality of clock lines;
• and
• wherein when an abnormality is detected by the monitoring and controlling means, the CPU either disconnects a first switching means of a first communication card currently providing the clock to the selected clock line and connects a first switching means of a second communication card to said selected clock line to provide a different clock to the selected clock line or controls the selecting means to select a different clock line.