Method of correcting single errors

Abstract

Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit positions. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.

Dependencies are inferred from the claim text.