US 5,631,913 A · Test circuit and test method of integrated semiconductor device

Abstract

In a test circuit of an integrated semiconductor device such as a memory, a parallel-input linear feedback shift register (LFSR) is used for both compressing data and comparing the obtained compressed value with an expected compressed value, thereby judging whether or not the integrated semiconductor device under test is normal. The parallel-input LFSR comprises a plurality of registers, a plurality of 2-input exclusive-OR gates placed in the stages previous to the respective registers mentioned above, and a feedback information generating means for generating feedback information from the output from the final-stage register and from the output from the register in a specified middle stage. In testing the integrated semiconductor device, the parallel-input LFSR compresses sequential sets of data from the integrated semiconductor device so as to obtain a compressed signature and then supplies the first input of the 2-input exclusive-OR gate placed in the leftmost position with the output from the final-stage register, while supplying the first inputs of the other exclusive-OR gates with the outputs from the registers in their respective previous stages. The second input of each of the exclusive-OR gates is supplied with an expected signature. Thus, the compressed value is compared with the expected compressed value at the respective exclusive-OR gates of the parallel-input LFSR.

Claims24

Dependent claims

A test circuit for testing an integrated semiconductor device, said test circuit comprising:

means for storing an expected compressed value;
a calculating circuit for compressing sequential sets of parallel data and obtaining a compressed value and also, for comparing said expected compressed value with a compressed value obtained from said sequential sets of parallel data;
an information collecting means for supplying, to said calculating circuit, sequential sets of parallel data obtained from an integrated semiconductor device under test and for supplying to said calculating circuit the compressed valued obtained by said calculating means and the expected compressed value stored in said expected compressed value storing means,
wherein said calculating circuit functions as a comparing means for comparing said obtained compressed value with the expected compressed value, and also for compressing data from said integrated semiconductor device under test during a normal operation of the integrated semiconductor device.

1 more element

A method for testing an integrated semiconductor device, comprising the steps of:

repeatedly compressing sequential sets of parallel data by reading sequential sets of data from the integrated semiconductor device in accordance with the same sequential addresses as supplied in generating an expected compressed value that has previously been obtained, while inputting the sequential sets of read data in parallel to the individual registers of a parallel-input linear feedback shift register, and shifting the sets of inputted data, so that the outputs from the individual registers at the time of compressing the final set of parallel data are obtained as the compressed value of the parallel data;
then supplying the first input of a 2-input exclusive-OR gate placed in the stage previous to the register in the first stage with the output from the register in the final stage and supplying the first inputs of 1-input exclusive-OR gates placed in the stages previous to the respective registers except the register in the first stage with the outputs from the registers in their respective previous stages;
inputting the expected compressed value to the second input of each of the 2-input exclusive-OR gates of said parallel-input linear feedback shift register;
and
comparing the compressed value of the parallel data with the expected compressed value bit by bit correspondingly at the 2-input exclusive-OR gates and judging, based on the result of comparison, whether or not the integrated semiconductor device under test is normal.

2 more elements

Dependencies are inferred from the claim text.

Test circuit and test method of integrated semiconductor device

Life of this patent

Test circuit and test method of integrated semiconductor device

Life of this patent

Abstract

Claims24