High impedance test mode for JTAG

A JTAG test circuit architecture for selectively enabling and disabling peripheral connections to an integrated circuit (IC), said architecture comprising:

• a boundary scan latch register including a plurality of data bit locations in electrical communication with said peripheral connections and in electrical communication with a plurality of output enable bit locations, each of said output enable bit locations used to enable the output of data bits stored in multiple ones of said data bit locations, wherein information stored in said output enable bit locations selectively places a plurality of said peripheral connections in a high impedance mode to selectively disable electrical communication between said data bit locations and said peripheral connections;
• and
• a boundary scan shift register which connects to said latch register so that contents of said shift register are parallel loaded into said latch register, said shift register including shift register data bit locations corresponding to said plurality of data bit locations in said latch register and including shift register output enable bit locations corresponding to said output enable bit locations in said latch register, said shift register output enable bit locations being grouped in close logical proximity within said shift register so that said shift register output enable bit locations are logically spaced apart by fewer shift register locations than the number of data bit locations enabled by each of said output enable bit locations;
• and
• a switching circuit which provides a first path through only said shift register output enable bit locations in close logical proximity while said switching circuit is in a first state, and which provides a second path through said shift register output enable bit locations and through said shift register data bit locations while said switching circuit is in a second state, said first path permitting states of said shift register output enable bit locations to be changed without changing states of said shift register data bit locations.