Integrated test circuit
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel, Jr.
Life of this patent
Estimating the term…
Abstract
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.
Claims16
A boundary scan test cell comprising, first and second memories and first and second multiplexers, wherein a first one of the inputs of the first multiplexer is connected to a serial data terminal (SDD, the input of the first memory is connected to the output of the first multiplexer, the input of the second memory is connected to an output of the first memory, first and second ones of the inputs of the second multiplexer are connected to an output of the second memory and a circuit data terminal respectively, characterized in that a second one of the inputs of the first multiplexer is connected to a circuit data terminal along a path that does not pass through the second multiplexer, that terminal being either the said circuit data terminal or a different circuit data terminal, and in that a third one of the inputs of the first multiplexer is connected to an inverted output of the second memory along a path that does not pass through the second multiplexer.
Dependencies are inferred from the claim text.