Information processing system provided with self-diagnosing circuit and the self-diagnosing method therefor

A method of testing an information processing system provided with a test circuit which is operable in a normal mode and a test operation mode, comprising:

• (a) a first step of reading and decoding testing microinstructions from memory for storing testing microinstructions, at a rising edge of a first clock signal in the test operation mode;
• (b) a second step of generating test data corresponding to the microinstructions decoded at the first step from a test data generating circuit, at the rising edge of the first clock signal, then transferring the test data to first type functional blocks to be tested or outputting data stored in second type functional blocks in the test operation mode;
• and
• (c) a third step of reading out test results transferred from the first type functional blocks at the second step into a data compressing circuit in order to compress the test results, or of storing test results derived from the test data in the first type functional blocks, at the falling edges of the first clock signal in the test operation mode, wherein
• (d) a cycle time of a basic clock signal for controlling the operation of the first and second type functional blocks in the normal operation mode being substantially the same as that of the first clock signal,
• the cycle time of the basic clock signal for controlling the operation of the first and second type functional blocks in the normal operation mode being 1/N times (N-2, 3, . . . ) as short as the first and second clock signals in the test operation mode, With the second clock signal being inverted in phase to the first clock signal by a delay of less than one cycle of the first clock signal.

An information processing system composed of a plurality of circuit blocks to be tested by a test, operative in a first operation mode and in a second operation mode, comprising:

• (a) clock signal generating means for generating a basic clock signal from a clock input signal in the first operation mode, a first clock signal with a cycle time N times (N=2, 3 . . . ) as long as than that of the basic clock signal, and a second clock signal out of phase with the first clock signal by a delay of less than one cycle of the first clock signal from the clock input signal in the second operation mode;
• (b) memory means for storing microinstructions for testing, operative in synchronism with the basic clock signal in the first operation mode, and in synchronism with the first clock signal in the second operation mode;
• (c) decoding means for receiving and decoding from the memory means in the second operation mode the microinstructions;
• (d) test data generating means for generating test data in accordance with the decoded results obtained by said decoding means in synchronism with the first clock signal in the second operation mode;
• (e) first type circuit blocks operative in synchronism with the basic clock signal in the first operation mode, for receiving test data generated by said test data generating means in synchronism with the second clock signal and outputting the test data therein in synchronism with the first clock signal in the second operation mode,
• (f) second type circuit blocks for receiving the test data generated by the data generating means in synchronism with the second clock signal, and for outputting output data in response to the data provided in synchronism with the basic clock signal in the first operation mode, and for outputting test result data in response to the test data provided from the test data generating means in synchronism with the first clock signal in the second operation mode;
• and
• (g) signature compressing means for receiving the test result data output from said first and second circuit blocks in order to test the operation of said first and second circuit blocks, in synchronism with the basic clock signal in the first operation mode, and in synchronism with the second clock signal in the second operation mode.

An information processing system composed of a plurality of circuit blocks to be tested by a test, operative in a first operation mode and in a second operation mode, comprising:

• (a) clock signal generating means for generating a basic clock signal from a clock input signal in the first operation mode, and the basic clock signal and an inversion clock signal to the basic clock signal;
• (b) memory means for storing microinstructions for testing, operative in synchronism with the basic clock signal in the first operation mode and the second operation mode;
• (c) decoding means for receiving the microinstruction and decoding the microinstructions for testing stored in said memory means,
• (d) test data generating means for generating test data in accordance with decoded results obtained by said decoding means in synchronism with the basic clock signal in the first operation mode and the second operation mode;
• (e) first type circuit blocks operative in synchronism with the basic clock signal in the first operation mode, for receiving test data generated by said test data generating means in synchronism with the inverted clock signal of the basic clock signal and outputting test data therein in synchronism with the basic clock signal in the second operation mode;
• (f) second type circuit blocks for receiving the test data generated by the data generating means in synchronism with the inverted clock signal, and for outputting output data in response to the data provided in synchronism with the basic clock signal in the first operation mode and for outputting test result data in response to the test data provided from the test data generating means in synchronism with the basic clock signal in the second operation mode;
• and
• (g) signature compressing means for receiving the test result data output from said first and second circuit blocks in order to test the operation of said first and second circuit blocks, in synchronism with the basic clock signal in the first operation mode, and in synchronism with the inverted clock signal of the basic clock signal in the second operation mode.

An information processing system composed of a plurality of circuit blocks operative in a first operation mode and in a second operation mode, comprising:

• (a) two external clock input terminals for receiving a basic clock signal in the first operation mode, and one terminal for receiving a first clock signal and the other terminal for inputting a second clock signal which is out of phase with the first clock signal by a delay of less than one cycle of the first clock signal;
• (b) memory means for storing microinstructions for testing, operative in synchronism with the basic clock signal in the first operation mode, and in synchronism with the first clock signal in the second operation mode;
• (c) decoding means for receiving and decoding the microinstructions for testing stored in said memory means;
• (d) test data generating means for generating test data in accordance with the decoded results obtained by said decoding means in synchronism with the first clock signal in the second operation mode;
• (e) first type circuit blocks operative in synchronism with the basic clock signal in the first operation mode, for receiving test data generated by said test data generating means in synchronism with the second clock signal and outputting test data therein in synchronism with the first clock signal in the second operation mode,
• (f) second type circuit blocks for receiving the test data generated by the data generating means in synchronism with the second clock signal, and for outputting output data in response to the data provided in synchronism with the basic clock signal in the first operation mode and for outputting test result data in response to the test data provided from the test data generating means in synchronism with the first clock signal in the second operation mode;
• and
• (g) signature compressing means for receiving the test result data output from said first and second circuit blocks in order to test the operation of said first and second circuit blocks, in synchronism with the basic clock signal in the first operation mode, and in synchronism with the second clock signal in the second operation mode.

An information processing system operative in a first operation mode and in a second operation mode, comprising:

• first means for outputting test data in synchronism with a first clock signal in the first operation mode and in synchronism with a second clock signal in the second operation mode;
• and
• a circuit block to be tested for receiving the test data from the first means and outputting result data in the second operation mode;
• and
• second means for inputting the result data from the circuit block in synchronism with the first clock signal in the first operation mode, and operative in synchronism with a third clock signal in the second operation mode,
• wherein the third clock signal is out of phase with the second clock signal by a delay of less than one cycle of the first clock signal.

An information processing system operative in a first operation mode and in a second operation mode, comprising:

• first means for outputting test data in synchronism with a first clock signal in the first operation mode, and operative in synchronism with a second clock signal in the second operation mode;
• a circuit block to be tested for receiving the test data from the first means and outputting test result data;
• and
• second means for receiving the test result data from the circuit block in synchronism with the first clock signal in the first operation mode and in synchronism with a third clock signal in the second operation mode,
• wherein the second clock signal is out of phase with the third clock signal by a delay of less than one of the third clock signal.