Hitless path switching apparatus and method

A hitless path switching apparatus which receives substantially the same line signals incoming through a first path and a second path in the form of a stream of data blocks each including an indicator for bit error checking, and supplies one of the line signals to a third path by hitless switching, thereby allotting one of the first path and the second path to a working path and the other to a protection path, said hitless path switching apparatus comprising:

• a first signal terminating circuit connected to said first path for receiving one of the substantially the same line signals and outputting a first line signal;
• a second signal terminating circuit connected to said second path for receiving the other of the substantially the same line signals and outputting a second line signal;
• a first bit error detecting circuit for detecting a bit error of each data block of said first line signal using said indicator for bit error checking;
• a second bit error detecting circuit for detecting a bit error of each data block of said second line signal using said indicator for bit error checking;
• a first delay circuit for delaying said first line signal by at least one data block interval;
• a second delay circuit for delaying said second line signal by at least one data block interval;
• a phase difference detecting circuit for detecting a phase difference between said first line signal and said second line signal;
• a phase adjusting circuit for adjusting the phase difference detected by said phase difference detecting circuit to match phases of said two line signals, and supplying in-phase data blocks of said first line signal and of said second line signal to said first delay circuit and said second delay circuit, respectively;
• a switching circuit for selectively supplying said third path with one of said first line signal outputted from said first delay circuit and said second line signal outputted from said second delay circuit;
• and
• a correlation monitoring circuit for supplying said switching circuit with a switching control signal to make said switching circuit supply said third path with said second line signal outputted from said second delay circuit, if said first bit error detecting circuit detects a bit error in a data block of said first line signal and said second bit error detecting circuit detects no bit error in a corresponding data block of said second line signal when said first path is allotted to said working path and said second path is allotted to said protection path.