Semiconductor memory
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKazutami Arimoto
Life of this patent
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Abstract
A semiconductor memory comprising memory cells, a write buffer, a write inversion gate, a data input terminal, and four write data buses 1-4. The write buffer and the write inversion gate place onto two write data buses 1 and 3 the data input through the data input terminal. The inverted data of the input data is output onto two other write data buses 2 and 4. This causes alternately different data to be written to four contiguous memory cells. The scheme permits detection of a cell fault caused by interference between contiguous memory cells.
Claims10
A semiconductor memory having a test mode, comprising:
- a memory array including a plurality of memory cells arranged in matrix fashion;
- selecting means for selecting two memory cells of said memory array in said test mode;
- writing means for generating a second signal by inverting an externally applied first signal, and for writing in parallel said first and second signals to the two memory cells selected by said selecting means;
- reading means for reading in parallel two signals from said two memory cells;
- and
- a test circuit for inverting either one of the two signals read by said reading means, and for determining that said two memory cells are normal when logic of the inverted signal coincides with logic of the other signal.
A semiconductor memory having a test mode, comprising:
- a memory array including a plurality of memory cells arranged in matrix fashion;
- selecting means for selecting in said test mode, from said memory array a plurality of contiguously arranged memory cells;
- writing means for generating a second signal by inverting an externally applied first signal, and for writing a first and a second signal parallelly to said contiguously arranged memory cells selected by said selecting means so that, of every two memory cells of said contiguous memory cells, one will store said first signal and the other said second signal;
- reading means for reading parallelly a plurality of signals from said contiguously arranged memory cells;
- and
- a test circuit for inverting, of the plurality of signals read by said reading means, the signal read from the memory cell to which one of said first and second signals is written and for determining that the plurality of memory cells are normal when logic of the signal read from the memory cell to which the other signal has been written coincides with the logic of said inverted signal.
Dependencies are inferred from the claim text.