Method and apparatus for testing redundant word and bit lines in a memory array
AssigneeInternational Business Machines Corporation
InventorsLuigi Termullo, Jr., Marcel J. Robillard, James J. Covino, Stuart J. Hall
Life of this patent
Estimating the term…
Abstract
A method and apparatus for evaluating a memory having memory elements and redundant memory elements for redundancy replacement. The redundant memory elements are tested to determine the number of good redundant memory elements. The memory elements are also tested to determine whether there are any failing memory elements. It is then determined whether a sufficient number of good redundant elements are available to replace the failing memory elements. If an insufficient number of redundant memory elements are available, the testing is stopped.
Claims4
An array built-in self-testing (ABIST) circuit for memory arrays having redundant memory elements wherein a testing device tests memory elements in a memory array to determine if there are any failing memory elements, the ABIST circuit comprising:
- a plurality of fail storage latches equal in number to the number of redundant memory elements, each fail storage latch, when enabled, being set upon detection of a failed memory element;
- a plurality of failed address storage registers each responsive to a corresponding fail storage latch for latching an address of a failed memory element upon the corresponding fail storage latch being set during ABIST testing;
- a first logic circuit responsive to a latched address in a failed address storage register and enabling a succeeding fail storage latch;
- individual redundant fail storage latches for each redundant memory element in the memory array, said testing device additionally testing each of the redundant elements during ABIST testing, the redundant fail storage latches being latched upon detection of a corresponding failed redundant memory element;
- a second logic circuit responsive to setting of any one of said redundant fail storage latches for bypassing a corresponding fail storage latch and enabling a succeeding fail storage latch;
- and
- a final fail latch enabled by said first and second logic circuits when a combination of redundant element failures and memory array element failures equals a total number of redundant memory elements, said final fail latch, when set, indicating failure of the memory array being tested.
Dependencies are inferred from the claim text.