Data outputting circuit for semiconductor memory device
AssigneeFujitsu Limited
InventorsAkihiro Iwase, Masaharu Kagohashi
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Abstract
A semiconductor memory device includes a sense amplifier and a load circuit which are connected to a pair of data buses through which cell data is read. The sense amplifier produces an output data signal in accordance with voltage potentials of transfer signals on the data buses. During data reading operation of the memory device, the sense amplifier is enabled and the transfer signals on the data buses have a different voltage potential level from each other. The load circuit sets the data buses at a predetermined reset voltage potential in a stand by state of the data reading operation. The reset voltage potential is intermediate of the voltage potential levels of the data buses when the sense amplifier is enabled.
Claims14
A semiconductor memory device, provided with a pair of data buses through which cell data is read, said memory device comprising:
- a sense amplifier, connected to said pair of data buses, for producing an output data signal in accordance with voltage potentials of transfer signals on said pair of data buses;
- and
- a load circuit, connected to said pair of data buses, for setting said data buses at a predetermined reset voltage potential during a stand-by state of said memory device, wherein said predetermined reset voltage potential is intermediate between different voltage potential levels of said transfer signals on said data buses during a data reading operation of said memory device.
A data outputting circuit for a semiconductor memory device, said data outputting circuit couples to a pair of data buses associated with said memory device, said data outputting circuit comprising:
- a sense amplifier, connected to said pair of data buses, for producing an output data signal in accordance with voltage potentials on said data buses;
- and
- a load circuit, connected to said pair of data buses, for setting said data buses at a predetermined reset voltage potential during a stand-by state of said memory device,
- wherein said data outputting circuit operates in data read mode and a stand-by mode,
- wherein during the stand-by mode, said predetermined reset voltage potential set on said data buses is between the voltage potential levels of said data buses during the data reading mode, and
- wherein during the data reading mode, said sense amplifier is enabled and said data buses have a different voltage potential level from each other in accordance with data from the semiconductor memory device.
Dependencies are inferred from the claim text.