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US 5,631,863 AGranted
Random access memory cell resistant to radiation induced upsets
AssigneeHoneywell Inc.
InventorsPaul S. Fechner, Gregor D. Dougal, Keith W. Golke
Life of this patent
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Abstract
A radiation resistant random access memory cell which has a coupling circuit between a storage node of a first CMOS pair and a gate node of a second CMOS pair. The coupling circuit is controlled by a word line and provides a first resistive element between the storage node and the body of the coupling circuit and a second resistive element between the gate node and the body of the coupling circuit.
Claims9
A CMOS memory cell, comprising:
- a first P-channel FET device connected between a first storage node and a relatively positive voltage and a first N channel FET device connected between said first storage node and a relatively negative voltage, with the gates of said first P channel and said first N channel devices connected in common at a first gate node and with said first storage node selectively connected to a first output line by a word line signal;
- a second P-channel FET device connected between a second storage node and said relatively positive voltage and a second N channel FET device connected between said second storage node and said relatively negative voltage, with the gates of said second P channel and said second N channel devices connected in common at a second gate node and with said second storage node selectively connected to a second output line by said word line signal;
- and
- at least a first coupling means having a first terminal connected to said word line signal, a second terminal connected to said first storage node, a third terminal connected to said second gate node, and a first body isolated from said relatively positive voltage and said relatively negative voltage, said first coupling means further having a first resistive means connected between said first coupling means second terminal and said first body, and a second resistive means connected between said first coupling means third terminal and said first body.
1 more element
A CMOS memory cell comprising:
- a first inverter having a first input and a first output, said first output selectively coupled to a first output line;
- a second inverter having a second input and a second output, said second output connected to said first input and selectively coupled to a second output line;
- and
- a first transistor having a first terminal connected to a word line signal, a second terminal connected to said first output, a third terminal connected to said second input, and an isolated body, said first transistor having a first resistive means between said second terminal and said isolated body and a second resistive means between said third terminal and said isolated body.
1 more element
Dependencies are inferred from the claim text.