Floating point arithmetic unit having logic for quad precision arithmetic

A method to effectuate quad precision arithmetic on a computer having double precision hardware including a double precision memory, and double precision buses, and a floating point unit having double-extended precision registers and a double-extended arithmetic logic unit, comprising the steps of:

• (a) convert a first portion of a quad precision quantity into a first low order word of a double double-extended representation of said quad precision quantity;
• (b) convert a second portion of said quad precision quantity into a first high order word of said double double-extended representation of said quad precision quantity;
• (c) using said double-extended precision arithmetic logic unit to perform at least one double-extended precision arithmetic operation on said first high order word and on said first low order word utilizing an algorithm for obtaining quad precision results represented by a second low order double-extended precision number and a second high order double-extended precision number;
• (d) convert said second low order word and said second high order word to a high part of a result quad precision quantity;
• and
• (e) convert said second low order word and said second high order word to a low part of said result quad precision quantity.

An apparatus for performing quad precision arithmetic, comprising:

• (a) a memory having double precision word width;
• (b) a register file having double-extended word width;
• (c) a load unit operable to transfer values from said memory to said register file;
• (d) an arithmetic logic unit operable to perform arithmetic operations on double-extended quantities stored in said register file;
• (e) a set of muxes connected to said arithmetic logic unit and operable to selectively transfer bits between a quad precision format and a double double-extended format;
• (f) a control unit connected to said register file, said arithmetic logic unit, and said muxes;
• and
• (g) a micro code memory connected to said control unit and containing instructions for converting a quad precision quantity into a pair of double-extended quantities.

A general purpose computer, comprising:

• (a) a central processing unit (CPU);
• (b) a memory connected to said CPU and capable of storing quantities in quad precision;
• and
• (c) a floating point unit (FPU) connected to said CPU, having:
• 1. a register file connected to said memory and capable of storing double-extended precision quantifies;
• 2. an arithmetic logic unit connected to said register file and capable of carrying out arithmetic operations on double-extended precision quantities;
• 3. a set of data muxes connected to said control unit and to said arithmetic logic unit and operable to convert a quad precision quantity into two double-extended quantities;
• 4. a rounding incrementer connected to said arithmetic logic unit and operable to round a double-extended quantity according to any of a plurality of rounding modes;
• 5. a microcode memory containing instructions for converting a quad precision quantity into a pair of double-extended quantities, instructions for performing arithmetic operations on double-extended quantities, instructions for converting from a pair of double-extended quantities to a quad precision quantity, and instructions for rounding a pair of double-extended quantities;
• and
• 6. a control unit connected to said register file, to said arithmetic logic unit, said data muxes and said rounding incrementer, and controlled by microcode stored in said microcode memory to cause, selectively, said arithmetic logic unit to perform double-extended precision arithmetic operations, said set of data muxes to convert a quad precision quantity into a pair of double-extended precision quantities, said rounding incrementer to round double-extended precision quantities and quad precision quantities represented as a pair of double-extended precision quantities using one of several rounding modes.

A method of performing arithmetic at a first precision in a computer having a memory having a plurality of cells, each cell storing a value, said computer having second precision hardware including a second precision memory, and second precision buses, and a floating point unit having extended second precision registers and an extended second precision arithmetic logic unit, wherein quantities represent in said first precision contain 2n bits, quantities represented in said second precision contain n bits, and quantities in represented in said extended second precision contain more than n bits and less than 2n bits, comprising the steps of:

• (a) converting a first precision quantity into a first pair of extended second precision quantities and storing said first pair of extended second precision quantities into a first and a second extended second precision container;
• (b) performing at least one extended second precision arithmetic operations on said first pair of extended second precision quantities, thereby producing a second pair of extended second precision quantities, and storing the results in a third and a fourth extended second precision container;
• and
• (c) converting said second pair of extended second precision quantities into a second first precision quantity.