Test sequence optimization process for a circuit tester
AssigneeInternational Business Machines Corporation
InventorsSteven A. Keller, Jiann-Chang Lo, James C. Mahlbacher
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AssigneeInternational Business Machines Corporation
InventorsSteven A. Keller, Jiann-Chang Lo, James C. Mahlbacher
Estimating the term…
The sequential order of movements of a number of probes within a circuit test fixture is optimized through the use of an algorithm which sequentially orders test configurations provided in an input list. Each test configuration corresponds to the locations of probes within the fixture as a particular test is performed. In a first pass of the algorithm, for each test configuration, every other test configuration is considered as a next move candidate for which a weighted distance is calculated from the test configuration. Weighting factors reflect the degree of difficulty in moving one direction instead of another. A need to move one probe before another or to move in one direction before another, in order to prevent a collision within the test fixture, is also considered. A predetermined number of next move candidates having the lowest weighted distances are placed in an intermediate list for the test configuration. In a second pass of the algorithm, test configurations are linked, one to another, to form a list reflecting a preferred order of probe movement. In the process of linking with a test configuration, the available next move candidate having the shortest weighted distance is chosen from the intermediate list of the test configuration. If no available next move candidates remain in the intermediate list, the process returns to the first pass of the algorithm to get more next move candidates. Additionally, the algorithm is used to sequentially order individual points for a test fixture having only a single probe.
A method for optimizing a sequence of test configurations within a circuit tester having structures movable between various of said test configurations, wherein said method comprises the steps of:
Apparatus for testing electrical circuits on a substrate, wherein said apparatus comprises:
Dependencies are inferred from the claim text.