System decoder circuit and method of operation

A data processing system for receiving and processing a bit sequence encoded using MPEG standard syntax, comprising:

• first in first out (FIFO) register circuitry operable to receive and store the data bits of the received bit sequence in words each comprising a plurality of data bits of the received bit sequence;
• shifter circuitry coupled to said FIFO register circuitry and operable to receive said words and to serially output bits within said received words;
• detector circuitry coupled to said shifter circuitry and operable to receive said bits output from said shifter circuitry and operable to detect predetermined bit patterns encoded in the bit sequence, said detector circuitry further operable to output in parallel selected groups of bits detected within the bit sequence;
• control logic circuitry coupled to said shifter circuitry and said detector circuitry and operable to direct the operation of said shifter and detector circuitries;
• buffer interface circuitry coupled to said detector circuitry and operable to receive said selected groups of bits output by said detector circuitry;
• shift counter circuitry coupled to said shifter and said control logic circuitries and operable to store a shift count value and operable to decrement said shift count value as said shifter circuitry serially outputs bits to said detector circuitry, said control logic circuitry operable to load a predetermined shift count value into said shift counter circuitry such that said control logic circuitry is able to specify a length of a particular bit sequence to be loaded into said detector circuitry using said predetermined shift count value;
• said control logic operable to receive information indicating the encoding layer of the bit sequence being received by the system;
• and
• said control logic circuitry and said detector circuitry operable to detect a start code within the bit sequence indicating the beginning of a packet of encoded data, said control logic circuitry and said detector circuitry further operable to detect presentation time stamps within the bit sequence.

A method for receiving and processing a bit sequence, comprising:

• receiving and storing the data bits of the received bit sequence in words in a first in first out (FIFO) register circuitry, each of the words comprising a plurality of data bits of the received bit sequence;
• receiving the words in shifter circuitry coupled to the FIFO register circuitry and serially outputting the bits within the received words from the shifter circuitry;
• receiving the bits output from the shifter circuitry into detector circuitry coupled to the shifter circuitry and detecting predetermined bit patterns encoded in the bit sequence, and outputting in parallel selected groups of bits detected within the bit sequence;
• directing the operation of the shifter and detector circuitries using control logic circuitry coupled to the shifter circuitry and the detector circuitry;
• and
• receiving and storing the selected groups of bits output by the detector circuitry in buffer interface circuitry coupled to the detector circuitry.