Video processor with field memory for exclusively storing picture information

A video processor comprising:

• a field memory;
• means for detecting a blanking interval of an incoming composite video signal and disabling read/write operations of said field memory during said blanking interval and enabling the read/write operations of the memory at other times so that field picture information of said incoming video signal is exclusively stored into, and read out of, the field memory into an external circuit;
• and
• means for alternately multiplexing a pedestal level signal with a synchronization level signal and supplying the multiplexed signal to said external circuit when the memory is disabled.

A video processor comprising:

• a system clock source for producing a system clock pulse;
• an analog-to-digital converter for converting an analog composite video signal to a digital bit sequence in response to the system clock pulse;
• a memory connected to said analog-to-digital converter;
• sync separator means for producing a horizontal synchronizing pulse and a vertical synchronizing pulse from said analog composite video signal;
• control means, responsive to said system clock pulse and said horizontal and vertical synchronizing pulses, for detecting a horizontal blanking interval and a vertical blanking interval and for disabling read/write operations of said memory during said horizontal and vertical blanking intervals and for enabling the read/write operations of the memory at other times so that a digital bit sequence of said analog-to-digital converter representing picture information of a field of said video signal is exclusively stored into, and read out of, the memory;
• and
• a digital-to-analog converter for converting the digital bit sequence representing the picture information from the memory to analog form in response to said system clock pulse.

A video processor comprising:

• a system clock source for producing a system clock pulse;
• an analog-to-digital converter for converting an analog composite video signal to a digital bit sequence in response to the system clock pulse;
• a memory connected to said analog-to-digital converter;
• sync separator means for producing a horizontal synchronizing pulse and a vertical synchronizing pulse from said analog composite video signal;
• control means responsive to said system clock pulse and said horizontal and vertical synchronizing pulses for detecting a horizontal blanking interval and a vertical blanking interval and disabling read/write operations of said memory during said horizontal and vertical blanking intervals and enabling the read/write operations of the memory at other times so that a digital bit sequence of said analog-to-digital converter representing picture information of a field of said video signal is exclusively stored into and read out of the memory;
• a digital-to=analog converter for converting the digital bit sequence representing the picture information from the memory to analog form in response to said system clock pulse;
• and
• means for alternatively multiplexing a digital pedestal level signal and a digital synchronization level signal and supplying the multiplexed signals to said digital-to-analog converter when the memory is disabled.

A video processor comprising:

• a clock source for producing a first clock pulse at a system clock rate and a second clock pulse at a rate equal to an integral submultiple of the system clock rate;
• a first analog-to-digital converter for converting an analog luminance (Y) signal of a composite video signal to a digital Y signal in response to the first clock pulse;
• second and third analog-to-digital converters for converting an analog R-Y color difference signal and an analog B-Y color difference signal, respectively, of said composite video signal to a digital R-Y color difference signal and a digital B-Y color difference signal in response to the second clock pulse;
• a parallel-to-serial converter for converting the digital R-Y color difference signal and the digital B-Y color difference signal to a pair of bit-serial signals having the same rate as the output of said first analog-to-digital converter;
• a memory connected to said first analog-to-digital converter and said parallel-to-serial converter;
• sync separator means for producing a horizontal synchronizing pulse and a vertical synchronizing pulse from said composite video signal;
• control means connected to be responsive to said first clock pulse from said clock source and to said horizontal and vertical synchronizing pulses from said sync separator means for detecting a horizontal blanking interval and a vertical blanking interval of said composite video signal and disabling read/write operations of said memory during said horizontal and vertical blanking intervals and enabling the read/write operations of the memory at other times so that field picture information of said digital Y signal from the first analog-to-digital converter and of the pair of bit-serial signals from the parallel-to-serial converter are exclusively stored into, and read out of, the memory;
• a first digital-to-analog converter for converting the picture information from the memory in response to said first clock pulse;
• a serial-to-parallel converter for converting the pair of stored bit-serial signals to a pair of bit-parallel signals;
• and
• second and third digital-to-analog converters for respectively converting the bit-parallel signals from the serial-to-parallel converter to analog form in response to said second clock pulse.

A video processor comprising:

• a clock source for producing a first clock pulse at a system clock rate and a second clock pulse at a rate equal to an integral submultiple of the system clock rate;
• a first analog-to-digital converter for converting an analog luminance (Y) signal of a composite video signal to a digital Y signal in response to the first clock pulse;
• second and third analog-to-digital converters for converting an analog R-Y color difference signal and an analog B-Y color difference signal, respectively, of said composite video signal to a digital R-Y color difference signal and a digital B-Y color difference signal in response to the second clock pulse;
• a parallel-to-serial converter for converting the digital R-Y color difference signal and the digital B-Y color difference signal to a pair of bit-serial signals having the same rate as the output of said first analog-to-digital converter;
• a memory connected to said first analog-to-digital converter and said parallel-to-serial converter;
• sync separator means for producing a horizontal synchronizing pulse and a vertical synchronizing pulse from said composite video signal;
• control means connected to be responsive to said first clock pulse from said clock source and to said horizontal and vertical synchronizing pulses from said sync separator means for detecting a horizontal blanking interval and a vertical blanking interval of said composite video signal and disabling read/write operations of said memory during said horizontal and vertical blanking intervals and enabling the read/write operations of the memory at other times so that field picture information of said digital Y signal from the first analog-to-digital converter and of the pair of bit-serial signals from the parallel-to-serial converter are exclusively stored into, and read out of, the memory;
• a first digital-to-analog converter for converting the picture information from the memory in response to said first clock pulse;
• a serial-to-parallel converter for converting the pair of stored bit-serial signals to a pair of bit-parallel signals;
• second and third digital-to-analog converters for respectively converting the bit-parallel signals from the serial-to-parallel converter to analog form in response to said second clock pulse;
• and
• means for alternately multiplexing a digital pedestal level signal and a digital synchronization level signal and supplying the multiplexed signals to second and third digital-to-analog converters when the memory is disabled.