Self-timed real-time data transfer in video-RAM

A Video-RAM memory device that performs a self-timed real-time data transfer, comprising:

• a RAM array;
• a serial access array having a serial output port;
• an address input for inputting addresses;
• sensing means for detecting a stimulus from an external controller indicating a selected coarse timing interval for a data transfer between the RAM array and the serial access array;
• a tap pointer for counting the pixels output from the serial output port;
• control logic for providing control signals that are synchronized with a serial clock and that occur during the coarse timing interval at a point that the tap pointer is equal to a programmable target value, wherein the control logic outputs one or more control signals, in response to the sensing means detecting the stimulus, commanding a data transfer between the RAM array and the serial access array to occur during the selected coarse timing interval, but wherein the data transfer is exactly timed internally by the control signals and not the stimulus;
• and
• transfer gates for transferring data between the RAM and the serial access array in response to control signals provided by the control logic.

A method of self-timed real-time data transfer within a Video-RAM device having a RAM, a serial access memory, and a tap pointer, the method comprising the steps of:

• transferring an initial row of pixels from the RAM to the serial access memory after receiving an initial external signal from an external controller, wherein the first row of pixels is serially transferred out of the serial access memory in synchronization with a serial clock;
• in response to receiving a subsequent external signal from the external controller, internally calculating, within the Video-RAM, a timing interval during which the initial row of pixels will complete its transfer out of the serial access memory;
• generating a control signal within the Video-RAM that occurs during the calculated timing interval and that is synchronized with the serial clock;
• and
• performing an accurate and synchronized transfer of a subsequent row of pixels from the RAM to the serial access memory in response to the control signal wherein the timing interval is calculated to be when the tap pointer is equal to a programmable target value.

A Video-RAM memory device having self-timed real-time data transfer, comprising:

• a RAM array;
• a serial access array having a serial output port, wherein a row of pixels loaded into the serial access array is serially transferred out of the serial access array in synchronization with a serial clock;
• an address input for inputting addresses;
• sensing means for detecting an external signal from an external controller;
• timing means for internally calculating a timing interval when a loaded row of pixels will complete its transfer out of the serial access memory, wherein the calculation is made in response to detecting an external signal;
• control logic for generating a control signal within the Video-RAM that occurs during the calculated timing interval and is synchronized with the serial clock;
• and
• transfer gates for accurately loading a row of pixels from the RAM to the serial access array in synchronization with the control signal wherein the timing means comprises a tap pointer and calculates a timing interval to be when the tap pointer is equal to a programmable target value.