Sample/hold free most significant bit comparator using bisection comparators

An analog to digital converter, comprising:

• a buffer;
• an input voltage;
• a number of fine analog to digital converters each said fine analog to digital converter having a fine input node and a fine output node wherein said fine input nodes are connected to said input voltage and said fine output nodes are connected to said buffer;
• and
• a number of bisection comparators for coarse analog to digital conversion wherein each said bisection comparator comprises:
• a VDD voltage node;
• a VSS voltage node;
• a reference voltage node;
• a course output node;
• a first node;
• a second node;
• an intermediate node;
• a first P Channel MOS field effect transistor having a first gate, a first source, and a first drain wherein said first source is connected to said VDD voltage node, said first drain is connected to said first node, said first node is connected to said intermediate node, and said first gate is connected to said input voltage;
• a second N Channel MOS field effect transistor having a second gate, a second source, and a second drain wherein said second source is connected to said VSS voltage node, said second drain is connected to said first node, and said second gate is connected to said first gate of said first P Channel MOS field effect transistor;
• a third P Channel MOS field effect transistor having a third gate, a third source, and a third drain wherein said third source is connected to said VDD voltage node, said third drain is connected to said second node, said second node is connected to said intermediate node, and said third gate is connected to said reference voltage node;
• a fourth N Channel MOS field effect transistor having a fourth gate, a fourth source, and a fourth drain wherein said fourth source is connected to said VSS voltage node, said fourth drain is connected to said second node, and said fourth gate is connected to said reference voltage node;
• a fifth P Channel MOS field effect transistor having a fifth gate, a fifth source, and a fifth drain wherein said fifth source is connected to said VDD voltage node, said fifth drain is connected to said coarse output node, and said fifth gate is connected to said intermediate node;
• and
• a sixth N Channel MOS field effect transistor having a sixth gate, a sixth source, and a sixth drain wherein said sixth source is connected to said VSS voltage node, said sixth drain is connected to said fifth drain of said fifth P Channel MOS field effect transistor, and said sixth gate is connected to said intermediate node.