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US 5,631,597 AGranted
Negative voltage circuit for a flash memory
AssigneeFujitsu Limited
InventorsTakao Akaogi, Hiromi Kawashima, Tetsuji Takeguchi, Ryoji Hagiwara, Yasushi Kasa, Kiyoshi Itano, Yasushige Ogawa, Shouichi Kawamura
Life of this patent
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Abstract
A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.
Claims5
A negative-voltage bias circuit comprising:
- a capacitor having first and second terminals;
- a first p-channel MIS field-effect transistor whose drain is connected to a negative-voltage output terminal and whose gate and source are connected to said first terminal of said capacitor;
- and
- a second p-channel MIS field-effect transistor whose drain is connected to the source of said first p-channel MIS field effect transistor, whose gate is connected to said negative-voltage output terminal, and whose source is provided with a negative voltage;
- wherein when a clock pulse is supplied to said second terminal of said capacitor during output of a negative-voltage, a potential of said negative-voltage output terminal is set to that of said negative voltage, and
- wherein said first p-channel MIS field-effect transistor is a depletion-type p-channel MIS field-effect transistor.
3 more elements
Dependencies are inferred from the claim text.