Process monitor for CMOS integrated circuits
AssigneeLSI Logic Corporation
InventorsNicholas Sporck, Teh-Kuin Lee
Life of this patent
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Abstract
A process for evaluating acceptability of a digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the process comprising: generating a leading edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating a trailing edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating an accepted-rejected signal, functionally related to the width of the pulse.
Claims22
A process for evaluating acceptability of a CMOS digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the process comprising:
- generating a first pulse having a first pulse width dependent on circuit elements of the first type with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type;
- generating a second pulse having a second pulse width dependent on circuit elements of the second type with the pulse generation circuit;
- determining the width of each pulse;
- comparing the width of each pulse to a predetermined value;
- and
- generating an accepted-rejected signal, wherein said generating is dependent upon said comparison.
A system for evaluating acceptability of a CMOS digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the system comprising:
- a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type, the pulse generation circuit generating;
- a first pulse having a first pulse width dependent on circuit elements of the first type and
- a second pulse having a second pulse width dependent on circuit elements of the second type;
- and
- an accepted-rejected signal generator having a comparator of the width of each pulse to a predetermined value, wherein said accepted-rejected signal is functionally related to the comparison.
A process monitor circuit comprising:
- a first delay unit having a first delay unit input and a first delay unit output;
- a second delay unit having a second delay unit input and a second delay unit output;
- a NAND gate having a first NAND gate input, a second NAND gate input, and a NAND gate output;
- a XOR gate having a first XOR gate input, a second XOR gate input, and a XOR gate output;
- wherein the output of the first delay unit is connected to the second delay unit input and the first XOR gate input;
- wherein the output of the second delay unit is connected to the second XOR gate input and the second NAND gate input through a second NAND gate input path;
- wherein the NAND gate output is connected to the first delay unit;
- wherein upon the application of a transition signal at the first NAND gate input, there results at the XOR gate output at least two pulses, the width of the first pulse being related to the response of the circuit to a first transition at the NAND gate output of the NAND gate, and the width of the second pulse being related to the response of the circuit to a second transition at the NAND gate output.
Dependencies are inferred from the claim text.