Pulse generation/sensing arrangement for use in a microprocessor system

A pulse generation arrangement for use in a microprocessor system, the arrangement comprising:

• an output node for producing thereat an output signal;
• timer means for producing time values;
• output register means for holding values corresponding to pulse edges to be generated;
• comparator means for comparing the values held in the output register means with time values produced by the timer means;
• and
• bistable means coupled to the output node for generating at the output node a signal whose state changes in response to the comparator means;
• wherein the output register means comprises a first register for holding a value corresponding to a first edge to be generated;
• a second register for holding a value corresponding to a second edge to be generated;
• and a third register for holding the value from the first register while the first register's value is updated.

A pulse generation and sensing arrangement for use in a microprocessor system, the arrangement comprising:

• an input/output node for receiving thereat an input signal in a first mode of operation and for producing thereat an output signal in a second mode of operation;
• edge detection means coupled to the input/output node for sensing pulse edges in the input signal in the first mode of operation;
• timer means for producing time values;
• register means having a first register, a second register and a third register arranged such that
• in the first mode of operation
• the first register holds a time value produced by the timer means corresponding to a first edge detected by the edge detection means;
• the second register holds a time value produced by the timer means corresponding to a second edge detected by the edge detection means;
• and the third register holds the value from the first register while the first register's value is updated;
• and
• in the second mode of operation
• the first register holds a value corresponding to a first edge to be generated;
• the second register holds a value corresponding to a second edge to be generated;
• and the third register holds the value from the first register while the first register's value is updated;
• comparator means for comparing the values held in the output register means in the second mode of operation with time values produced by the timer means;
• and
• bistable means coupled to the output node for generating at the input/output node in the second mode of operation a signal whose state changes in response to the comparator means.