Method and apparatus for synchronizing timing signals of two integrated circuit chips

A phase synchronization circuit comprising:

• a phase comparator having a first input terminal coupled to a first bus clock line, a second input terminal coupled to a second bus clock line, a first output terminal coupled to a first trigger line and a second output terminal coupled to a second trigger line, the phase comparator further including a phase lock detect circuit having a control input terminal coupled to a clear line and a control output terminal coupled to a frequency switch;
• a delay circuit having a first input terminal coupled to the first trigger line, a second input terminal coupled to the second trigger line, a first output terminal coupled to a first source clock line, a second output terminal coupled to a second source clock line, a clock input terminal coupled to a clock line, a control input terminal coupled to a reset line and a control output terminal coupled to the dear line;
• and
• said frequency switch having a clock signal input terminal coupled to a system oscillator, a clock signal output terminal coupled to the clock line, and a control input terminal coupled to said output terminal of said phase lock detect circuit.

A method of synchronizing timing signals of two integrated circuits comprising the steps of:

• detecting a system reset signal:
• enabling a low frequency temporary oscillator and disabling a system oscillator:
• sensing a rising edge of a first bus clock signal and a second bus clock signal;
• comparing a relative phase of the first and second bus clock signals to determine a leading bus clock signal;
• identifying the leading bus clock signal to be a preempted bus clock signal;
• monitoring the first and second bus clock signals to identify a plurality of preempted bus clock signals;
• detecting rising edges of a plurality of preempted bus clock signals;
• for each rising edge of the plurality of preempted bus clock signals, incrementing a delay of a source clock timing signal corresponding to the preempted bus clock signal;
• comparing a relative phase of the first and second bus clock signals;
• terminating further delaying of the source clock timing signal when the relative phase of the first and second bus clock signals match;
• and
• disabling the low frequency temporary oscillator and enabling the system oscillator.

A method of synchronizing timing signals of two integrated circuits comprising the steps of:

• detecting a system reset signal;
• enabling a low frequency temporary oscillator and disabling a system oscillator;
• sensing a rising edge of a first bus clock signal and a second bus clock signal;
• comparing a relative phase of the first and second bus clock signals to determine a leading bus clock signal;
• determining whether the relative phase of the first and second bus clock signals is greater than 180.degree.;
• when the relative phase of the first and second bus clock signals is greater than 180.degree., rough synchronizing the first and second bus clock signals by eliminating one source clock cycle from one signal of the first and second bus clock signals;
• identifying the leading bus clock signal to be a preempted bus clock signal;
• monitoring the first and second bus clock signals to identify a plurality of preempted bus clock signals;
• detecting rising edges of the plurality of preempted bus clock signals;
• for each rising edge of the plurality of preempted bus clock signal rising edges, incrementing a delay of a source clock timing signal corresponding to the preempted bus clock signal;
• comparing a relative phase of the first and second bus clock signals;
• terminating further delaying of the source clock timing signal when the relative phase of the first and second bus clock signals match;
• and
• disabling the low frequency temporary oscillator and enabling the system oscillator.

A phase synchronization circuit comprising:

• means for detecting a system reset signal;
• means for enabling a low frequency temporary oscillator and disabling a system oscillator:
• means for sensing a rising edge of a first bus clock signal and a second bus clock signal;
• a phase comparator for comparing a relative phase of the first and second bus clock signals to determine a leading bus clock signal;
• means for identifying the leading bus clock signal to be a preempted bus clock signal;
• means for monitoring the first and second bus clock signals to identify a plurality of preempted bus clock signals;
• means for detecting rising edges of a plurality of preempted bus clock signals;
• means operative for the rising edges of the plurality of preempted bus clock signal rising edges for incrementing a delay of a source clock timing signal corresponding to the preempted bus clock signal;
• means for comparing a relative phase of the first and second bus clock signals;
• means for terminating further delaying of the source clock timing signal when the relative phase of the first and second bus clock signals match;
• and
• means for disabling the low frequency temporary oscillator and enabling the system oscillator.

An electronic circuit comprising:

• a first integrated circuit chip having a source clock input terminal coupled to a first source clock line and a bus clock output terminal coupled to a first bus clock line;
• a second integrated circuit chip having a source clock input terminal coupled to a second source clock line and a bus clock output terminal coupled to a second bus clock line;
• a phase comparator having a first input terminal coupled to the first bus clock line, a second input terminal coupled to the second bus clock line, a first output terminal coupled to a first trigger line and a second output terminal coupled to a second trigger line, the phase comparator generating trigger signals on the first and second trigger lines responsive to bus timing signals on the first and second bus clock lines indicative of a propagation delay in the first and second integrated circuit chips;
• a first adjustable delay line having an input terminal coupled to the first trigger line, an output terminal coupled to the first source clock line, and a clock input terminal coupled to a system clock line;
• a second adjustable delay line having an input terminal coupled to the second trigger line, an output terminal coupled to the second source clock line, and a clock input terminal coupled to the system clock line;
• the first and second adjustable delay lines generating source clock signals on the first and second source clock lines so that an additional delay is added to the source clock signals of a chip selected from the first and second integrated circuit chips, the selected chip having a smaller propagation delay;
• and
• a frequency switch having an input terminal coupled to the phase comparator and a clock signal output terminal coupled to the system clock line, the frequency switch locking a system clock signal generated on the system clock line responsive to a signal from the phase comparator indicative that the propagation delay in the first and second integrated circuit chips is substantially equal.