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US 5,631,590 AGranted
Synchronized clock signal regenerating circuit
AssigneeFujitsu Limited
InventorNobuaki Tomesakai
Life of this patent
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Abstract
A clock signal regenerating circuit includes a first PLL circuit, a PLL part circuit which forms a second PLL circuit in cooperation with the first PLL circuit, the second PLL circuit performing a frequency-synchronizing operation on a clock signal and a data signal. The first PLL circuit performs a phase-synchronizing operation on the clock signal and an output signal of the PLL part circuit. The phase-synchronizing operation has a speed lower than that of the frequency-synchronizing operation.
Claims9
A clock signal regenerating circuit comprising:
- a first PLL circuit;
- a PLL part circuit connected to an output of said first PLL circuit, said PLL part circuit forming a second PLL circuit, the second PLL circuit performing a phase-synchronizing operation on a clock signal output from said first PLL circuit and a data signal input to said PLL part circuit, the first PLL circuit performing a frequency-synchronizing operation on the clock signal and an output signal of said PLL part circuit, said clock signal being taken as an output of the clock signal regenerating circuit,
- the phase-synchronizing operation having a speed lower than that of the frequency-synchronizing operation.
Dependencies are inferred from the claim text.