Frequency and phase comparator
AssigneeRohm Co., Ltd.
InventorAkio Fujikawa
Life of this patent
Estimating the term…
Abstract
A frequency and phase comparator has a first flip-flop and a second flip-flop. Logical calculation between the outputs of these flip-flops is performed by an AND circuit, and the first and second flip-flops are reset by the output of the logical calculation. The first and second flip-flops receive periodic signals at their clock terminals. When the periods of the output pulses of the first and second flip-flops are short, a circuit driven by the pulses sometimes cannot operate correctly. To prevent this, a pulse generating circuit is provided which receives a first periodic signal and a second periodic signal to generate a pulse signal of a predetermined width, and the pulse signal is added to the outputs of the first and second flip-flops.
Claims5
A frequency and phase comparator comprising:
- a first flip-flop having a reset terminal and receiving a first periodic signal at its clock terminal;
- a second flip-flop having a reset terminal and receiving a second periodic signal at its clock terminal;
- a logical circuit performing a logic calculation between an output of the first flip-flop and an output of the second flip-flop, said logical circuit resetting the first and second flip-flops with an output of the logical calculation;
- pulse generating means, having an input connected to only inputs of said first and second flip-flops, for receiving only the first and second periodic signals to output a pulse signal of a predetermined width when logical values of the first and second periodic signals become the same;
- pulse adding means for adding the pulse signal to each of the outputs of the first and second flip-flops;
- and
- outputting means for combining the pulse-signal-added outputs of the first and second flip-flops and outputting a combined signal.
A frequency and phase comparator comprising:
- a first flip-flop having a reset terminal and receiving a first periodic signal at its clock terminal;
- first delaying means for delaying an output of the first flip-flop by a predetermined time .tau..sub.1 ;
- a second flip-flop having a reset terminal and receiving a second periodic signal at its clock terminal;
- a second delaying means for delaying an output of the second flip-flop by a predetermined time .tau..sub.2 ;
- a logical circuit performing a logical calculation between an output of the first delaying means and an output of the second delaying means, said logical circuit resetting the first and second flip-flops with an output of the logical calculation;
- and
- outputting means for combining the outputs of the first and second delaying means,
- wherein said predetermined time .tau..sub.1 and said predetermined time .tau..sub.2 are so different from each other that a time required for transmitting the output of the first flip-flop to the outputting means is substantially equal to a time required for transmitting the output of the second flip-flop to the outputting means.
A frequency and phase comparator comprising:
- a first flip-flop having a reset terminal and receiving a first periodic signal at its clock terminal;
- first delaying means for delaying an output of the first flip-flop by a predetermined time .tau..sub.1 ;
- a second flip-flop having a reset terminal and receiving a second periodic signal at its clock terminal;
- a second delaying means for delaying an output of the second flip-flop by a predetermined time .tau..sub.2 ;
- a logical circuit which performs a logical calculation between an output of the first delaying means and an output of the second delaying means, said logical circuit resetting the first and second flip-flops with an output of the logical calculation;
- and
- outputting means for combining the outputs of the first and second flip-flops,
- wherein said predetermined time .tau..sub.1 and said predetermined time .tau..sub.2 are so different from each other that a time required for transmitting the output of the first flip-flop to the outputting means is substantially equal to a time required for transmitting the output of the second flip-flop to the outputting means.
Dependencies are inferred from the claim text.