Programmable array interconnect network

A programmable array having a plurality of logic cells arranged therein, the programmable array further having a programmable interconnect network including a first plurality of interconnect buses, the first plurality of interconnect buses being associated with, and running along, a row/column of logic cells of the plurality of logic cells, the first plurality of interconnect buses comprising:

• first and second pluralities of local buses, said first and second pluralities of local buses each comprising conductors, wherein the conductors in each of said first and second pluralities of local buses are selectively connectable to the logic cells of the row/column of logic cells for logic signal input to the cells and logic signal output from the cells;
• first and second pluralities of express buses, said first and second pluralities of express buses each comprising conductors, wherein the conductors in each of said first and second pluralities of express buses are generally electrically isolated from the logic cells of the row/column of logic cells and have lengths of less than the entire length of the row/column of logic cells;
• first and second long interconnect buses, said first and second long interconnect buses o being generally electrically isolated from the logic cells of the row/column of logic cells and each comprising a conductor having a length being longer than the conductors of the local and express buses;
• a first plurality of programmable elements for providing signals between selected pairs of the conductors of the first plurality of local buses, the first plurality of express buses, and the first long bus;
• and
• a second plurality of programmable elements for providing signals between selected pairs of the conductors of the second plurality of local buses, the second plurality of express buses, and the second long bus,
• wherein the first and second pluralities of programmable elements divide at least some of their respective buses into conductor lengths, the first and second pluralities of programmable elements each comprising:
• a plurality of programmable switches positioned at equivalent first intervals in the first plurality of interconnect buses;
• and
• a plurality of programmable jumpers connected within buses of the first and second pluralities of local buses for selectively connecting adjacent conductors thereof,
• wherein interior conductors of the first and second pluralities of local buses generally have lengths between programmable elements equal to the first interval and less than the first interval, and wherein interior conductors of the first and second pluralities of express buses generally have lengths between programmable elements equal to the first interval and greater than the first interval.

A programmable array having a plurality of logic cells arranged therein, the programmable array further having a programmable interconnect network including a first plurality of interconnect buses being associated with, and running along, a row/column of logic cells of the plurality of logic cells, the first plurality of interconnect buses comprising:

• first and second pluralities of local buses, said first and second pluralities of local buses each comprising conductors, wherein the conductors in each of said first and second pluralities of local buses are selectively connectable to the logic cells of the row/column of logic cells for logic signal input to the cells and logic signal output from the cells;
• first and second pluralities of express buses, said first and second pluralities of express buses each comprising conductors, wherein the conductors in each of said first and second pluralities of express buses are generally electrically isolated from the logic cells of the row/column of logic cells and have lengths of less than the entire length of the row/column of logic cells;
• first and second long interconnect buses, said first and second long interconnect buses being generally electrically isolated from the logic cells of the row/column of logic cells and each comprising a conductor having a length being longer than the conductors of the local and express buses;
• a first plurality of programmable elements for providing signals between selected pairs of the conductors of the first plurality of local buses, the first plurality of express buses, and the first long bus;
• and
• a second plurality of programmable elements for providing signals between selected pairs of the conductors of the second plurality of local buses, the second plurality of express buses and the second long bus,
• wherein the row/column of logic cells is arranged into sectors of logic cells, the sectors being defined by a first length being measurable in logic cell units, and wherein interior conductors of the first and second pluralities of local buses have lengths of lees than and equal to the first length and the conductors of the first and second pluralities of express buses have lengths of greater than and equal to the first length.

A programmable interconnect system for a programmable array having a plurality of logic cells arranged therein, the programmable interconnect system having a first plurality of interconnect buses (34a) associated with, and running along, a row/column of logic cells of the plurality of logic cells, the row/column of logic cells being divisible into at least two pluralities of contiguous logic cells, each plurality of the at least two pluralities of contiguous logic cells having a first selected number of logic cells therein, the first selected number of logic cells being greater than one, wherein the first plurality of interconnect buses comprises:

• a plurality of local buses, said plurality of local buses being connectable to logic cells of the row/column of logic cells, said plurality of local buses including a first plurality of conductors and a second plurality of conductors, the conductors of the first and second pluralities of conductors being interior conductors, wherein the conductors of the first plurality of conductors of the plurality of local buses have a length less than the first selected number of logic cells, and the conductors of the second plurality of conductors of the plurality of local buses have a length equal to the first selected number of logic cells;
• and
• a plurality of express buses, said plurality of express buses being generally electrically isolated from the logic cells of the row/column of logic cells, said plurality of express buses including a first plurality of conductors and a second plurality of conductors, the conductors of the first and second pluralities of conductors of the plurality of express buses being interior conductors, wherein the conductors of the first plurality of conductors of the plurality of express buses have a length equal to the first selected number of logic cells, and the conductors of the second plurality of conductors of the plurality of express buses have a length greater than the first selected number of logic cells and less than the length of the entire row/column of logic cells.

A programmable array having a plurality of logic cells arranged therein, said programmable array further having a programmable interconnect network including a plurality of interconnect buses, the plurality of interconnect buses being associated with, and running along, a row/column of logic cells of the plurality of logic cells, the plurality of interconnect buses comprising:

• a first group of buses (64a) including a first, second and third bus of a first, second and third type, respectively;
• a first plurality of programmable interior switches, separated by generally equivalent first intervals, for providing signals between conductors of the first and third buses, but not the second bus, of the first group of buses;
• a second plurality of programmable interior switches, separated by the generally equivalent first intervals, and offset from the first plurality of switches by at least the length of one logic cell, for providing signals between conductors of the first and second buses, but not the third bus, of the first group of buses;
• a second group of buses (64b) including a first, second and third bus of the first, second and third types, respectively;
• and
• a third plurality of programmable interior switches, corresponding in position to the first plurality of programmable switches, for providing signals between conductors of the first and second buses, but not the third bus, of the second group of buses;
• and
• a fourth plurality of programmable interior switches, corresponding in position to the second plurality of switches, for providing signals between conductors of the first and third buses, but not the second bus, of the second group of buses such that a staggered switching pattern results in which the second buses are not interrupted by either the first or fourth pluralities of switches and the third buses are not interrupted by either the second or third pluralities of switches.