Programmable logic array integrated circuit devices with flexible carry chains

A programmable logic array integrated circuit comprising:

• a plurality Of logic modules, each of which is programmable to produce sum out signal carry out signal;
• indicative of the and array out from addition of two addend signals and carry in signal applied to that logic module;
• programmable network of interconnection conductors for programmably selectively connecting outputs of said logic modules to inputs of said logic modules, said programmable network comprising:
• a plurality of subnetworks of local interconnection conductors, each of said subnetworks being associated with a respective subplurality of said logic modules for programmably selectively connecting outputs of said logic modules in said subplurality to inputs of said logic modules in said subplurality, and
• a network of global interconnection conductors for programmably selectively connecting outputs of any of said logic modules inputs of substantially any of said logic modules;
• a carry chain conductor extending between each pair of said logic modules for conducting a carry out signal from one of said logic modules in said pair to the other logic module in said pair for possible use is carry an signal by said other logic module in said pair;
• first programmable logic circuitry associated with each of said logic modules for selectively substituting a signal on one of said inputs to said logic module which is connected to said programmable network of interconnection conductors for the carry in signal received by that logic module via a carry chain conductor;
• and
• second programmable logic circuitry associated with each of said logic modules for selectively applying the carry out signal of said logic module to one of said outputs of said logic module which is connected to said programmable network of interconnection conductors, said second programmable logic circuitry comprising:
• a first subcircuit for selectively applying to a first output of said logic module either the sum out or the carry out signal of said logic module, said first output being connected to the subnetwork of local interconnection conductors which is associated with the subplurality of logic modules that includes said logic module, and
• a second subcircuit for selectively applying to a second output of said logic module either the sum out or the carry out signal of said logic module, said second output being connected to the network of global conductors.

A programmable logic array integrated circuit comprising:

• a plurality of logic modules, each of which is programmable to produce a sum out signal and a carry out signal indicative of the sum and carry out from addition of two addend signals and a carry in signal applied to that logic module;
• a programmable network of interconnection conductors for programmably selectively connecting outputs of said logic modules to inputs of said logic modules;
• a carry chain conductor extending between each pair of said logic modules for conducting a carry out signal from one of said logic modules in said pair to the other logic module in said pair for possible use as a carry in signal by said other logic module in said pair;
• first programmable logic circuitry associated with each of said logic modules for selectively substituting a signal on one of said inputs to said logic module which is connected to said programmable network of interconnection conductors for the carry in signal received by that logic module via a carry chain conductor, said first programmable logic circuitry comprising:
• a programmable element for producing an output signal indicative of whether a signal on one of said inputs to said logic module or the carry in signal received by that logic module via a carry chain conductor is to be used by that logic module as its carry in signal,
• carry out signal precursor processing circuitry responsive to the output signal of said programmable element for passing through two carry out signal precursor signals if said output signal of said programmable element indicates that said carry in signal received via a carry chain conductor is to be used, said carry out signal precursor processing circuitry being further responsive to the signal on said one of said inputs to said logic module by substituting one of said carry out signal precursor signals, as selected by the signal on said one of said inputs to said logic module, for the other of said carry out signal precursor signals in the two signals passed through by said carry out signal precursor processing circuitry, and
• carry out signal precursor selection circuitry responsive to said carry in signal received by said logic module via a carry chain conductor for selecting said carry out signal of said logic module from the two signals passed through by said carry out signal precursor processing circuitry;
• and
• second programmable logic circuitry associated with each of said logic modules for selectively applying the carry out signal of said logic module to one of said outputs of said logic module which is connected to said programmable network of interconnection conductors.