Intermediate voltage sensor for CMOS circuits

An intermediate voltage sensor for CMOS circuits comprising:

• a first linear inverter having an output end and an input end which is connected with an input signal under test;
• a second linear inverter having an output end and input end which is connected with said output end of said first linear inverter;
• a voltage control switch having a control end, an input end and an output end, with said control end being connected with said input end of said first linear inverter, and with input end being connected with said output end of said second linear inverter;
• and
• a buffer being opposite in characteristic to said first linear inverter and said second linear inverter such that said buffer having a precipitous switching characteristic, said buffer provided with an input end which is connected with said output end of said voltage control switch;
• wherein said buffer is capable of giving forth an output voltage having a first logic value when said input signal has a voltage value of logic "0" or logic "1";
• and wherein said buffer is capable of giving forth another output voltage having a second logic value when said input signal has a voltage value intermediate between said logic "0" and said logic "1", with said second logic value being different from said first logic value.

An intermediate voltage sensor for CMOS circuits comprising:

• a first positive logic voltage control switch having an output end and a control end which is connected with an input signal under test;
• an inverter having an output end and an input end which is connected with said output end of said first positive logic voltage control switch
• a first negative logic voltage control switch having an output end, an input end which is connected with said output end of said inverter, and a control end which is connected with said input signal under test;
• and
• a buffer having a precipitous switching characteristic and provided with an input end which is connected with output end of said first negative logic voltage control switch;
• wherein said buffer is capable of giving forth an output voltage having a first logic value when said input signal has a voltage value of logic "0" or logic "1";
• and wherein said buffer is further capable of giving forth another output voltage having a second logic value when said input signal has a voltage value intermediate between said logic "0" and said logic "1".