Power semiconductor device with low on-state voltage

A semiconductor device comprising:

• a first main terminal;
• a second main terminal having a voltage different from the voltage of the first main terminal;
• a control terminal;
• a first voltage control semiconductor element for conducting the flow of a main current therethrough, one of the main electrodes of the first control semiconductor element being connected to the first main terminal, the other main electrode being connected to the second main terminal;
• a second voltage control semiconductor element having both of a current capacity and a saturated current per unit area smaller than those of the first voltage control semiconductor element, one of the main electrodes of the second control semiconductor element being connected to the first main terminal, the other main electrode being connected to the second main terminal through a resistance, the control electrode being connected to the control terminal, wherein the second voltage control semiconductor element permits the flow of a fraction of the main current therethrough and operates to detect a possible overcurrent flowing through the first voltage control semiconductor element;
• a switching element, a pair of the main electrodes of the switching element being connected to the control terminal and the second main terminal, the control electrode being connected to the junction point of the other main electrode of the second voltage control semiconductor element and the resistance, wherein the switching element is turned on when the voltage developed across the resistance caused by the current flowing through the second voltage control semiconductor element exceeds a given value and decreases a control voltage applied to the control electrodes of the first and the second voltage control semiconductor elements;
• and
• a delay element connected between the control electrode of the first voltage control semiconductor element and the control electrode of the second voltage control semiconductor element, wherein the delay element delays the turning-on of the first voltage control semiconductor element to be after the turning-on of the second voltage control semiconductor element when an ON-signal is applied to the control terminal.

A semiconductor device comprising:

• a first main terminal;
• a second main terminal having a voltage different from the voltage of the first main terminal;
• a control terminal;
• an insulated gate bipolar transistor for conducting the flow of a main current therethrough, of which the collector electrode is connected to the first main terminal, the emitter electrode being connected to the second main terminal;
• a MOS transistor having both of a current capacity and a saturated current per unit area smaller than the insulated gate bipolar transistor, the drain electrode of the MOS transistor being connected to the first main terminal, the source electrode being connected to the second main terminal through a resistance, wherein the MOS transistor permits the flow of a fraction of the main current therethrough and operates to detect a possible overcurrent flowing through the insulated gate bipolar transistor;
• a switching element, a pair of the main electrodes of the switching element being connected to the control terminal and the second main terminal, the control electrode being connected to the junction point of the source electrode of the MOS transistor and the resistance, wherein the switching element is turned on when the voltage developed across the resistance caused by the current flowing through the MOS transistor exceeds a given value and decreases a control voltage applied to the gate electrodes of the insulated gate bipolar transistor and the MOS transistor;
• and
• a delay element connected between the gate electrode of the insulated gate bipolar transistor and the gate electrode of the MOS transistor, wherein the delay element delays the turning-on of the insulated gate bipolar transistor to be after the turning-on of the MOS transistor when an ON-signal is applied to the control terminal.

A semiconductor device comprising:

• a first main terminal;
• a second main terminal having a voltage different from the voltage of the first main terminal;
• a control terminal;
• A MOS gate turn-off thyristor for conducting the flow of a main current therethrough, of which the anode electrode is connected to the first main terminal, the cathode electrode being connected to the second main terminal, wherein the insulated gate bipolar transistor permits the flow of a fraction of the main current therethrough and operates to detect a possible overcurrent flowing through the MOS gate turn-off thyristor;
• an insulated gate bipolar transistor having both of an current capacity and a saturated current per unit area smaller than those of the MOS gate turn-off thyristor, the collector electrode of the insulated gate bipolar transistor being connected to the first main terminal, the emitter electrode being connected to the second main terminal through a resistance;
• a gate circuit being connected between the second main terminal and the control terminal, putting out a positive control signal when the voltage at the junction point of the emitter electrode of the insulated gate bipolar transistor and the resistance is lower than a given value, putting out a negative control signal when the voltage at the junction point of the emitter electrode of the insulated gate bipolar transistor and the resistance is higher than the given value;
• a delay element connected between the gate electrode of the MOS gate turn-off thyristor and the gate electrode of the insulated gate bipolar transistor, wherein the delay element delays the turning-on of the MOS gate turn-off thyristor to be after the turning-on of the insulated gate bipolar transistor when an ON-signal is applied to the control terminal.

A semiconductor device comprising:

• a first main terminal;
• a second main terminal having a voltage different from the voltage of the first main terminal;
• a control terminal;
• a first insulated gate bipolar transistor, of which the collector electrode is connected to the first main terminal, the emitter electrode being connected to the second main terminal;
• a second insulated gate bipolar transistor having both of a current capacity and a saturated current per unit area smaller than the first insulated gate bipolar transistor, the collector electrode of the second insulated gate bipolar transistor being connected to the first main terminal, the emitter electrode being connected to the second main terminal through a first resistance;
• a switching element, a pair of the main electrodes of the switching element being connected to the control terminal and the second main terminal, the control electrode being connected to the junction point of the emitter electrode of the second insulated gate bipolar transistor and the first resistance;
• a delay element connected between the gate electrode of the first insulated gate bipolar transistor and the gate electrode of the second insulated gate bipolar transistor;
• a third insulated gate bipolar transistor having both of a current capacity and a saturated current per unit area smaller than the first insulated gate bipolar transistor, the collector electrode of the third insulated gate bipolar transistor being connected to the first main terminal, the emitter electrode being connected to the second main terminal through a second resistance, the gate electrode being connected to the gate electrode of the first insulated gate bipolar transistor;
• and
• means being connected between the second main terminal and the control terminal, putting out an OFF-control signal to the control terminal when the voltage at the junction point of the emitter electrode of the third insulated gate bipolar transistor and the second resistance is higher than a given value.