Method of manufacturing a semiconductor device and termination structure

A process for forming a vertical power MOSFET device comprising the steps of:

• providing a semiconductor substrate having a first and second major surface, wherein the semiconductor substrate is of a first conductivity type;
• forming a gate dielectric layer over the first major surface;
• forming a polycrystalline gate layer over the gate dielectric layer;
• forming a dielectric layer over the polycrystalline gate layer;
• patterning the dielectric layer, the polycrystalline gate layer, and the gate dielectric layer to form a first insulated gate region, a second insulated gate region and to form a first opening between the first and second insulated gate regions;
• forming a first base region in the semiconductor substrate self-aligned to the first and second insulated gate regions, wherein the first base region has a second conductivity type opposite the first conductivity type;
• forming a first source region in the first base region self-aligned to the first and second insulated gate regions, wherein the first source region has the first conductivity type;
• forming spacers in the first opening;
• forming a protective layer over the first major surface;
• patterning the protective layer to form a second opening within the first opening and a third opening above the second insulated gate region;
• removing a portion of the first major surface through the second opening;
• removing a portion of the dielectric layer through the third opening to expose a portion of the polycrystalline gate layer;
• forming a doped region of the second conductivity type in the first major surface self-aligned to the spacers;
• forming an ohmic layer over the first major surface;
• and
• patterning the ohmic layer to provide a source contact and a gate contact.

A vertical power MOSFET device comprising:

• a semiconductor substrate having a first conductivity type, a first major surface, a second major surface opposite the first major surface, and a first edge, wherein the second major surface forms a common drain;
• an active portion including an active base region of a second conductivity type extending from the first major surface into the semiconductor substrate and an active source region within the active base region, the active source region having the first conductivity type;
• and
• a termination portion including a first termination region extending from the first major surface into the semiconductor substrate between the first edge and the active portion and a first termination gate region disposed over the first major surface between the first termination region and the active portion, wherein the first termination region comprises a first termination base region of the first conductivity type and a first termination source region of the second conductivity type, and wherein the first termination region is electrically coupled to the first termination gate region and the common drain.

A method for forming a vertical power MOSFET device comprising the steps of:

• providing a semiconductor substrate having a first conductivity type, a first major surface, a second major surface opposite the first major surface, and a first edge, wherein the second major surface forms a common drain;
• forming an active portion including an active base region of a second conductivity type extending from the first major surface into the semiconductor substrate and an active source region within the active base region, the active source region having the first conductivity type;
• and
• forming a termination portion including a first termination region extending from the first major surface into the semiconductor substrate between the first edge and the active portion and a first termination gate region disposed over the first major surface between the first termination region and the active portion, wherein the first termination region comprises a first termination base region of the first conductivity type and a first termination source region of the second conductivity type, and wherein the first termination region is electrically coupled to the first termination gate region and the common drain.